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some ar531x cleanup

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SVN-Revision: 6302
This commit is contained in:
Felix Fietkau 2007-02-15 21:52:13 +00:00
parent e7697a9ab6
commit c13d383c2b
6 changed files with 2120 additions and 42 deletions
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24
target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.c
View file

@ -30,12 +30,6 @@
#include "ar531x.h"
#define AR531X_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
#define AR531X_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
#define AR531X_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
#define AR531X_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
#define AR531X_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
static struct platform_device *ar5312_devs[5];
@ -49,8 +43,8 @@ static struct resource ar5312_eth0_res[] = {
{
.name = "eth_irq",
.flags = IORESOURCE_IRQ,
.start = AR531X_IRQ_ENET0_INTRS,
.end = AR531X_IRQ_ENET0_INTRS,
.start = AR5312_IRQ_ENET0_INTRS,
.end = AR5312_IRQ_ENET0_INTRS,
},
};
@ -65,8 +59,8 @@ static struct resource ar5312_eth1_res[] = {
{
.name = "eth_irq",
.flags = IORESOURCE_IRQ,
.start = AR531X_IRQ_ENET1_INTRS,
.end = AR531X_IRQ_ENET1_INTRS,
.start = AR5312_IRQ_ENET1_INTRS,
.end = AR5312_IRQ_ENET1_INTRS,
},
};
@ -221,13 +215,13 @@ asmlinkage void ar5312_irq_dispatch(void)
int pending = read_c0_status() & read_c0_cause();
if (pending & CAUSEF_IP2)
do_IRQ(AR531X_IRQ_WLAN0_INTRS);
do_IRQ(AR5312_IRQ_WLAN0_INTRS);
else if (pending & CAUSEF_IP3)
do_IRQ(AR531X_IRQ_ENET0_INTRS);
do_IRQ(AR5312_IRQ_ENET0_INTRS);
else if (pending & CAUSEF_IP4)
do_IRQ(AR531X_IRQ_ENET1_INTRS);
do_IRQ(AR5312_IRQ_ENET1_INTRS);
else if (pending & CAUSEF_IP5)
do_IRQ(AR531X_IRQ_WLAN1_INTRS);
do_IRQ(AR5312_IRQ_WLAN1_INTRS);
else if (pending & CAUSEF_IP6) {
unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
@ -448,7 +442,7 @@ void __init ar5312_misc_intr_init(int irq_base)
irq_desc[i].chip = &ar5312_misc_intr_controller;
}
setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
setup_irq(AR531X_IRQ_MISC_INTRS, &cascade);
setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
}

11
target/linux/atheros-2.6/files/arch/mips/atheros/ar5312.h
View file

@ -13,6 +13,17 @@
#include <asm/addrspace.h>
/*
* IRQs
*/
#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
/* Address Map */
#define AR531X_WLAN0 0x18000000
#define AR531X_WLAN1 0x18500000

16
target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.c
View file

@ -28,12 +28,6 @@
#include <asm/io.h>
#include "ar531x.h"
#define AR531X_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
#define AR531X_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
#define AR531X_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
#define AR531X_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
#define AR531X_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
static struct resource ar5315_eth_res[] = {
{
.name = "eth_membase",
@ -44,8 +38,8 @@ static struct resource ar5315_eth_res[] = {
{
.name = "eth_irq",
.flags = IORESOURCE_IRQ,
.start = AR531X_IRQ_ENET0_INTRS,
.end = AR531X_IRQ_ENET0_INTRS,
.start = AR5315_IRQ_ENET0_INTRS,
.end = AR5315_IRQ_ENET0_INTRS,
},
};
@ -218,9 +212,9 @@ asmlinkage void ar5315_irq_dispatch(void)
int pending = read_c0_status() & read_c0_cause();
if (pending & CAUSEF_IP3)
do_IRQ(AR531X_IRQ_WLAN0_INTRS);
do_IRQ(AR5315_IRQ_WLAN0_INTRS);
else if (pending & CAUSEF_IP4)
do_IRQ(AR531X_IRQ_ENET0_INTRS);
do_IRQ(AR5315_IRQ_ENET0_INTRS);
else if (pending & CAUSEF_IP2) {
unsigned int ar531x_misc_intrs = sysRegRead(AR5315_ISR) & sysRegRead(AR5315_IMR);
@ -504,7 +498,7 @@ void ar5315_misc_intr_init(int irq_base)
irq_desc[i].chip = &ar5315_misc_intr_controller;
}
setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5315_ahb_proc_interrupt);
setup_irq(AR531X_IRQ_MISC_INTRS, &cascade);
setup_irq(AR5315_IRQ_MISC_INTRS, &cascade);
}
void __init ar5315_plat_setup(void)

42
target/linux/atheros-2.6/files/arch/mips/atheros/ar5315.h
View file

@ -12,6 +12,16 @@
#ifndef AR5315_H
#define AR5315_H
/*
* IRQs
*/
#define AR5315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
#define AR5315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
#define AR5315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
#define AR5315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
#define AR5315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
/*
* Address map
*/
@ -80,23 +90,23 @@
*/
#define AR5315_ENDIAN_CTL (AR5315_DSLBASE + 0x000c)
#define CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
#define CONFIG_WLAN 0x00000002 /* WLAN byteswap */
#define CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
#define CONFIG_PCI 0x00000008 /* PCI byteswap */
#define CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
#define CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
#define CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
#define AR5315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
#define AR5315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
#define AR5315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
#define AR5315_CONFIG_PCI 0x00000008 /* PCI byteswap */
#define AR5315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
#define AR5315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
#define AR5315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
#define CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
#define CONFIG_CPU 0x00000400 /* CPU big endian */
#define CONFIG_PCIAHB 0x00000800
#define CONFIG_PCIAHB_BRIDGE 0x00001000
#define CONFIG_SPI 0x00008000 /* SPI byteswap */
#define CONFIG_CPU_DRAM 0x00010000
#define CONFIG_CPU_PCI 0x00020000
#define CONFIG_CPU_MMR 0x00040000
#define CONFIG_BIG 0x00000400
#define AR5315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
#define AR5315_CONFIG_CPU 0x00000400 /* CPU big endian */
#define AR5315_CONFIG_PCIAHB 0x00000800
#define AR5315_CONFIG_PCIAHB_BRIDGE 0x00001000
#define AR5315_CONFIG_SPI 0x00008000 /* SPI byteswap */
#define AR5315_CONFIG_CPU_DRAM 0x00010000
#define AR5315_CONFIG_CPU_PCI 0x00020000
#define AR5315_CONFIG_CPU_MMR 0x00040000
#define AR5315_CONFIG_BIG 0x00000400
/*

41
target/linux/atheros-2.6/files/include/asm-mips/mach-atheros/dma-coherence.h Normal file
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@ -0,0 +1,41 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
*
*/
#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
#define PCI_DMA_OFFSET 0x20000000
struct device;
static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
{
return virt_to_phys(addr) + (dev != NULL ? PCI_DMA_OFFSET : 0);
}
static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
{
return page_to_phys(page) + (dev != NULL ? PCI_DMA_OFFSET : 0);
}
static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
{
return (dma_addr > PCI_DMA_OFFSET ? dma_addr - PCI_DMA_OFFSET : dma_addr);
}
static void plat_unmap_dma_mem(dma_addr_t dma_addr)
{
}
static inline int plat_device_is_coherent(struct device *dev)
{
return 0;
}
#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */

2028
target/linux/atheros-2.6/patches/150-mips_cache_cleanup.patch Normal file
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