Make this work with recent versions of SPI module
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cf7f9ec0cc
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1 changed files with 416 additions and 416 deletions
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@ -128,7 +128,7 @@ class MFRC522:
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serNum = []
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serNum = []
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def __init__(self, dev='/dev/spidev0.0', spd=1000000):
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def __init__(self, dev='/dev/spidev0.0', spd=1000000):
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spi.openSPI(device=dev,speed=spd)
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self.spidev = spi.openSPI(device=dev,speed=spd)
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GPIO.setmode(GPIO.BOARD)
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GPIO.setmode(GPIO.BOARD)
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GPIO.setup(self.NRSTPD, GPIO.OUT)
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GPIO.setup(self.NRSTPD, GPIO.OUT)
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GPIO.output(self.NRSTPD, 1)
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GPIO.output(self.NRSTPD, 1)
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@ -138,10 +138,10 @@ class MFRC522:
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self.Write_MFRC522(self.CommandReg, self.PCD_RESETPHASE)
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self.Write_MFRC522(self.CommandReg, self.PCD_RESETPHASE)
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def Write_MFRC522(self, addr, val):
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def Write_MFRC522(self, addr, val):
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spi.transfer(((addr<<1)&0x7E,val))
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spi.transfer(self.spidev, ((addr<<1)&0x7E,val))
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def Read_MFRC522(self, addr):
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def Read_MFRC522(self, addr):
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val = spi.transfer((((addr<<1)&0x7E) | 0x80,0))
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val = spi.transfer(self.spidev, (((addr<<1)&0x7E) | 0x80,0))
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return val[1]
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return val[1]
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def SetBitMask(self, reg, mask):
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def SetBitMask(self, reg, mask):
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