From 1f3d521b0a4d2e9997a4f536e372037244b2bda6 Mon Sep 17 00:00:00 2001 From: Mario Gomez Date: Mon, 1 Jul 2013 07:33:43 +0000 Subject: [PATCH] Added MFRC522 support --- MFRC522.py | 302 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 302 insertions(+) create mode 100644 MFRC522.py diff --git a/MFRC522.py b/MFRC522.py new file mode 100644 index 0000000..889700a --- /dev/null +++ b/MFRC522.py @@ -0,0 +1,302 @@ +import RPi.GPIO as GPIO +import spi +import signal + +class MFRC522: + NRSTPD = 22 + + MAX_LEN = 16 + + PCD_IDLE = 0x00 + PCD_AUTHENT = 0x0E + PCD_RECEIVE = 0x08 + PCD_TRANSMIT = 0x04 + PCD_TRANSCEIVE = 0x0C + PCD_RESETPHASE = 0x0F + PCD_CALCCRC = 0x03 + + PICC_REQIDL = 0x26 + PICC_REQALL = 0x52 + PICC_ANTICOLL = 0x93 + PICC_SElECTTAG = 0x93 + PICC_AUTHENT1A = 0x60 + PICC_AUTHENT1B = 0x61 + PICC_READ = 0x30 + PICC_WRITE = 0xA0 + PICC_DECREMENT = 0xC0 + PICC_INCREMENT = 0xC1 + PICC_RESTORE = 0xC2 + PICC_TRANSFER = 0xB0 + PICC_HALT = 0x50 + + MI_OK = 0 + MI_NOTAGERR = 1 + MI_ERR = 2 + + Reserved00 = 0x00 + CommandReg = 0x01 + CommIEnReg = 0x02 + DivlEnReg = 0x03 + CommIrqReg = 0x04 + DivIrqReg = 0x05 + ErrorReg = 0x06 + Status1Reg = 0x07 + Status2Reg = 0x08 + FIFODataReg = 0x09 + FIFOLevelReg = 0x0A + WaterLevelReg = 0x0B + ControlReg = 0x0C + BitFramingReg = 0x0D + CollReg = 0x0E + Reserved01 = 0x0F + + Reserved10 = 0x10 + ModeReg = 0x11 + TxModeReg = 0x12 + RxModeReg = 0x13 + TxControlReg = 0x14 + TxAutoReg = 0x15 + TxSelReg = 0x16 + RxSelReg = 0x17 + RxThresholdReg = 0x18 + DemodReg = 0x19 + Reserved11 = 0x1A + Reserved12 = 0x1B + MifareReg = 0x1C + Reserved13 = 0x1D + Reserved14 = 0x1E + SerialSpeedReg = 0x1F + + Reserved20 = 0x20 + CRCResultRegM = 0x21 + CRCResultRegL = 0x22 + Reserved21 = 0x23 + ModWidthReg = 0x24 + Reserved22 = 0x25 + RFCfgReg = 0x26 + GsNReg = 0x27 + CWGsPReg = 0x28 + ModGsPReg = 0x29 + TModeReg = 0x2A + TPrescalerReg = 0x2B + TReloadRegH = 0x2C + TReloadRegL = 0x2D + TCounterValueRegH = 0x2E + TCounterValueRegL = 0x2F + + Reserved30 = 0x30 + TestSel1Reg = 0x31 + TestSel2Reg = 0x32 + TestPinEnReg = 0x33 + TestPinValueReg = 0x34 + TestBusReg = 0x35 + AutoTestReg = 0x36 + VersionReg = 0x37 + AnalogTestReg = 0x38 + TestDAC1Reg = 0x39 + TestDAC2Reg = 0x3A + TestADCReg = 0x3B + Reserved31 = 0x3C + Reserved32 = 0x3D + Reserved33 = 0x3E + Reserved34 = 0x3F + + serNum = [] + + writeData = [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 100] + moneyConsume = 18 + moneyAdd = 10 + + sectorKeyA = [ + [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF], + [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF], + [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF], + ] + + sectorNewKeyA = [ + [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF], + [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xff,0x07,0x80,0x69, 0x19,0x84,0x07,0x15,0x76,0x14], + [0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xff,0x07,0x80,0x69, 0x19,0x33,0x07,0x15,0x34,0x14], + ] + + def __init__(self,spd=1000000): + spi.openSPI(speed=spd) + GPIO.setmode(GPIO.BOARD) + GPIO.setup(22, GPIO.OUT) + GPIO.output(self.NRSTPD, 1) + self.MFRC522_Init() + + def MFRC522_Reset(self): + self.Write_MFRC522(self.CommandReg, self.PCD_RESETPHASE) + + def Write_MFRC522(self,addr,val): + spi.transfer(((addr<<1)&0x7E,val)) + + def Read_MFRC522(self,addr): + val = spi.transfer((((addr<<1)&0x7E) | 0x80,0)) + return val[1] + + def SetBitMask(self, reg, mask): + tmp = self.Read_MFRC522(reg) + self.Write_MFRC522(reg, tmp | mask) + + def ClearBitMask(self, reg, mask): + tmp = self.Read_MFRC522(reg); + self.Write_MFRC522(reg, tmp & (~mask)) + + def AntennaOn(self): + temp = self.Read_MFRC522(self.TxControlReg) + if(~(temp & 0x03)): + self.SetBitMask(self.TxControlReg, 0x03) + + def AntennaOff(self): + self.ClearBitMask(self.TxControlReg, 0x03) + + def MFRC522_ToCard(self,command,sendData): + backData = [] + backLen = 0 + status = self.MI_ERR + irqEn = 0x00 + waitIRq = 0x00 + lastBits = None + n = 0 + i = 0 + + if command == self.PCD_AUTHENT: + irqEn = 0x12 + waitIRq = 0x10 + if command == self.PCD_TRANSCEIVE: + irqEn = 0x77 + waitIRq = 0x30 + + self.Write_MFRC522(self.CommIEnReg, irqEn|0x80) + self.ClearBitMask(self.CommIrqReg, 0x80) + self.SetBitMask(self.FIFOLevelReg, 0x80) + + self.Write_MFRC522(self.CommandReg, self.PCD_IDLE); + + while(i self.MAX_LEN: + n = self.MAX_LEN + + i = 0 + while i