2013-11-11 05:11:20 +00:00
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import RPi.GPIO as GPIO
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import spi
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import signal
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class MFRC522:
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NRSTPD = 22
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MAX_LEN = 16
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PCD_IDLE = 0x00
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PCD_AUTHENT = 0x0E
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PCD_RECEIVE = 0x08
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PCD_TRANSMIT = 0x04
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PCD_TRANSCEIVE = 0x0C
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PCD_RESETPHASE = 0x0F
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PCD_CALCCRC = 0x03
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PICC_REQIDL = 0x26
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PICC_REQALL = 0x52
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PICC_ANTICOLL = 0x93
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PICC_SElECTTAG = 0x93
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PICC_AUTHENT1A = 0x60
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PICC_AUTHENT1B = 0x61
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PICC_READ = 0x30
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PICC_WRITE = 0xA0
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PICC_DECREMENT = 0xC0
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PICC_INCREMENT = 0xC1
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PICC_RESTORE = 0xC2
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PICC_TRANSFER = 0xB0
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PICC_HALT = 0x50
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MI_OK = 0
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MI_NOTAGERR = 1
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MI_ERR = 2
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Reserved00 = 0x00
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CommandReg = 0x01
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CommIEnReg = 0x02
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DivlEnReg = 0x03
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CommIrqReg = 0x04
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DivIrqReg = 0x05
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ErrorReg = 0x06
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Status1Reg = 0x07
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Status2Reg = 0x08
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FIFODataReg = 0x09
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FIFOLevelReg = 0x0A
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WaterLevelReg = 0x0B
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ControlReg = 0x0C
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BitFramingReg = 0x0D
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CollReg = 0x0E
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Reserved01 = 0x0F
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Reserved10 = 0x10
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ModeReg = 0x11
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TxModeReg = 0x12
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RxModeReg = 0x13
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TxControlReg = 0x14
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TxAutoReg = 0x15
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TxSelReg = 0x16
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RxSelReg = 0x17
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RxThresholdReg = 0x18
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DemodReg = 0x19
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Reserved11 = 0x1A
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Reserved12 = 0x1B
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MifareReg = 0x1C
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Reserved13 = 0x1D
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Reserved14 = 0x1E
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SerialSpeedReg = 0x1F
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Reserved20 = 0x20
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CRCResultRegM = 0x21
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CRCResultRegL = 0x22
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Reserved21 = 0x23
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ModWidthReg = 0x24
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Reserved22 = 0x25
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RFCfgReg = 0x26
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GsNReg = 0x27
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CWGsPReg = 0x28
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ModGsPReg = 0x29
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TModeReg = 0x2A
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TPrescalerReg = 0x2B
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TReloadRegH = 0x2C
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TReloadRegL = 0x2D
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TCounterValueRegH = 0x2E
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TCounterValueRegL = 0x2F
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Reserved30 = 0x30
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TestSel1Reg = 0x31
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TestSel2Reg = 0x32
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TestPinEnReg = 0x33
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TestPinValueReg = 0x34
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TestBusReg = 0x35
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AutoTestReg = 0x36
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VersionReg = 0x37
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AnalogTestReg = 0x38
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TestDAC1Reg = 0x39
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TestDAC2Reg = 0x3A
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TestADCReg = 0x3B
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Reserved31 = 0x3C
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Reserved32 = 0x3D
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Reserved33 = 0x3E
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Reserved34 = 0x3F
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serNum = []
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def __init__(self,spd=1000000):
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spi.openSPI(speed=spd)
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GPIO.setmode(GPIO.BOARD)
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GPIO.setup(22, GPIO.OUT)
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GPIO.output(self.NRSTPD, 1)
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self.MFRC522_Init()
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def MFRC522_Reset(self):
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self.Write_MFRC522(self.CommandReg, self.PCD_RESETPHASE)
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def Write_MFRC522(self,addr,val):
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spi.transfer(((addr<<1)&0x7E,val))
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def Read_MFRC522(self,addr):
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val = spi.transfer((((addr<<1)&0x7E) | 0x80,0))
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return val[1]
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def SetBitMask(self, reg, mask):
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tmp = self.Read_MFRC522(reg)
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self.Write_MFRC522(reg, tmp | mask)
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def ClearBitMask(self, reg, mask):
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tmp = self.Read_MFRC522(reg);
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self.Write_MFRC522(reg, tmp & (~mask))
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def AntennaOn(self):
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temp = self.Read_MFRC522(self.TxControlReg)
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if(~(temp & 0x03)):
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self.SetBitMask(self.TxControlReg, 0x03)
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def AntennaOff(self):
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self.ClearBitMask(self.TxControlReg, 0x03)
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def MFRC522_ToCard(self,command,sendData):
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backData = []
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backLen = 0
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status = self.MI_ERR
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irqEn = 0x00
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waitIRq = 0x00
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lastBits = None
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n = 0
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i = 0
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if command == self.PCD_AUTHENT:
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irqEn = 0x12
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waitIRq = 0x10
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if command == self.PCD_TRANSCEIVE:
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irqEn = 0x77
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waitIRq = 0x30
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self.Write_MFRC522(self.CommIEnReg, irqEn|0x80)
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self.ClearBitMask(self.CommIrqReg, 0x80)
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self.SetBitMask(self.FIFOLevelReg, 0x80)
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2013-11-11 07:12:06 +00:00
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2013-11-11 05:11:20 +00:00
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self.Write_MFRC522(self.CommandReg, self.PCD_IDLE);
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2013-11-11 07:12:06 +00:00
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2013-11-11 05:11:20 +00:00
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while(i<len(sendData)):
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self.Write_MFRC522(self.FIFODataReg, sendData[i])
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i = i+1
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2013-11-11 07:12:06 +00:00
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self.Write_MFRC522(self.CommandReg, command)
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2013-11-11 05:11:20 +00:00
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if command == self.PCD_TRANSCEIVE:
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self.SetBitMask(self.BitFramingReg, 0x80)
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2013-11-11 07:12:06 +00:00
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2013-11-11 05:11:20 +00:00
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i = 2000
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while True:
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n = self.Read_MFRC522(self.CommIrqReg)
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i = i - 1
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if ~((i!=0) and ~(n&0x01) and ~(n&waitIRq)):
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2013-11-11 07:12:06 +00:00
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break
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2013-11-11 05:11:20 +00:00
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self.ClearBitMask(self.BitFramingReg, 0x80)
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if i != 0:
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if (self.Read_MFRC522(self.ErrorReg) & 0x1B)==0x00:
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2013-11-11 07:12:06 +00:00
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status = self.MI_OK
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if n & irqEn & 0x01:
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status = self.MI_NOTAGERR
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2013-11-11 05:11:20 +00:00
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2013-11-11 07:12:06 +00:00
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if command == self.PCD_TRANSCEIVE:
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n = self.Read_MFRC522(self.FIFOLevelReg)
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lastBits = self.Read_MFRC522(self.ControlReg) & 0x07
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if lastBits != 0:
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backLen = (n-1)*8 + lastBits
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else:
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backLen = n*8
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if n == 0:
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n = 1
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if n > self.MAX_LEN:
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n = self.MAX_LEN
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2013-11-11 05:11:20 +00:00
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2013-11-11 07:12:06 +00:00
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i = 0
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while i<n:
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backData.append(self.Read_MFRC522(self.FIFODataReg))
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i = i + 1;
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else:
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status = self.MI_ERR
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2013-11-11 05:11:20 +00:00
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return (status,backData,backLen)
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def MFRC522_Request(self, reqMode):
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status = None
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backBits = None
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TagType = []
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self.Write_MFRC522(self.BitFramingReg, 0x07)
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TagType.append(reqMode);
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(status,backData,backBits) = self.MFRC522_ToCard(self.PCD_TRANSCEIVE, TagType)
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if ((status != self.MI_OK) | (backBits != 0x10)):
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status = self.MI_ERR
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return (status,backBits)
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def MFRC522_Anticoll(self):
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backData = []
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serNumCheck = 0
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serNum = []
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self.Write_MFRC522(self.BitFramingReg, 0x00)
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serNum.append(self.PICC_ANTICOLL)
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serNum.append(0x20)
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(status,backData,backBits) = self.MFRC522_ToCard(self.PCD_TRANSCEIVE,serNum)
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if(status == self.MI_OK):
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i = 0
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if len(backData)==5:
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2013-11-11 07:12:06 +00:00
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while i<4:
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serNumCheck = serNumCheck ^ backData[i]
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i = i + 1
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if serNumCheck != backData[i]:
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status = self.MI_ERR
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2013-11-11 05:11:20 +00:00
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else:
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2013-11-11 07:12:06 +00:00
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status = self.MI_ERR
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2013-11-11 05:11:20 +00:00
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return (status,backData)
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def CalulateCRC(self, pIndata):
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self.ClearBitMask(self.DivIrqReg, 0x04)
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self.SetBitMask(self.FIFOLevelReg, 0x80);
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i = 0
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while i<len(pIndata):
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self.Write_MFRC522(self.FIFODataReg, pIndata[i])
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i = i + 1
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self.Write_MFRC522(self.CommandReg, self.PCD_CALCCRC)
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i = 0xFF
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while True:
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n = self.Read_MFRC522(self.DivIrqReg)
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i = i - 1
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if not ((i != 0) and not (n&0x04)):
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2013-11-11 07:12:06 +00:00
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break
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2013-11-11 05:11:20 +00:00
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pOutData = []
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pOutData.append(self.Read_MFRC522(self.CRCResultRegL))
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pOutData.append(self.Read_MFRC522(self.CRCResultRegM))
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return pOutData
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def MFRC522_SelectTag(self, serNum):
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backData = []
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buf = []
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buf.append(self.PICC_SElECTTAG)
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buf.append(0x70)
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i = 0
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while i<5:
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buf.append(serNum[i])
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i = i + 1
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pOut = self.CalulateCRC(buf)
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buf.append(pOut[0])
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buf.append(pOut[1])
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(status, backData, backLen) = self.MFRC522_ToCard(self.PCD_TRANSCEIVE, buf)
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2013-11-11 07:12:06 +00:00
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2013-11-11 05:11:20 +00:00
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if (status == self.MI_OK) and (backLen == 0x18):
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2013-11-11 07:12:06 +00:00
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print "Size: " + str(backData[0])
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return backData[0]
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2013-11-11 05:11:20 +00:00
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else:
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2013-11-11 07:12:06 +00:00
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return 0
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2013-11-11 05:11:20 +00:00
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def MFRC522_Auth(self, authMode, BlockAddr, Sectorkey, serNum):
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buff = []
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buff.append(authMode)
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buff.append(BlockAddr)
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i = 0
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2013-11-11 07:12:06 +00:00
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while(i < len(Sectorkey)):
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2013-11-11 05:11:20 +00:00
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buff.append(Sectorkey[i])
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i = i + 1
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i = 0
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2013-11-11 07:12:06 +00:00
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while(i < len(serNum)):
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2013-11-11 05:11:20 +00:00
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buff.append(serNum[i])
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i = i +1
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(status, backData, backLen) = self.MFRC522_ToCard(self.PCD_AUTHENT,buff)
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if not(status == self.MI_OK):
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print "AUTH ERROR!!"
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2013-11-11 07:12:06 +00:00
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if not (self.Read_MFRC522(self.Status2Reg) & 0x08) != 0:
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print "AUTH ERROR(status2reg & 0x08) != 0"
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return status
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2013-11-11 05:11:20 +00:00
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def MFRC522_Read(self, blockAddr):
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recvData = []
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recvData.append(self.PICC_READ)
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recvData.append(blockAddr)
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pOut = self.CalulateCRC(recvData)
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recvData.append(pOut[0])
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recvData.append(pOut[1])
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(status, backData, backLen) = self.MFRC522_ToCard(self.PCD_TRANSCEIVE, recvData)
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if not(status == self.MI_OK):
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2013-11-11 07:12:06 +00:00
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print "Error while reading!"
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2013-11-11 05:11:20 +00:00
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print "Got data size: "+str(backLen)
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i = 0
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if len(backData) == 16:
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2013-11-11 07:12:06 +00:00
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print "Sector "+str(blockAddr)+" "+str(backData)
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2013-11-11 05:11:20 +00:00
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def MFRC522_Write(self, blockAddr, writeData):
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buff = []
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buff.append(self.PICC_WRITE)
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buff.append(blockAddr)
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crc = self.CalulateCRC(buff)
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buff.append(crc[0])
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buff.append(crc[1])
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(status, backData, backLen) = self.MFRC522_ToCard(self.PCD_TRANSCEIVE, buff)
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if not(status == self.MI_OK) or not(backLen == 4) or not((backData[0] & 0x0F) == 0x0A):
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2013-11-11 07:12:06 +00:00
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status = self.MI_ERR
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print str(backLen)+" backdata &0x0F == 0x0A "+str(backData[0]&0x0F)
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2013-11-11 05:11:20 +00:00
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if status == self.MI_OK:
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2013-11-11 07:12:06 +00:00
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i = 0
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buf = []
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while i < 16:
|
|
|
|
buf.append(writeData[i])
|
|
|
|
i = i + 1
|
|
|
|
crc = self.CalulateCRC(buf)
|
|
|
|
buf.append(crc[0])
|
|
|
|
buf.append(crc[1])
|
|
|
|
(status, backData, backLen) = self.MFRC522_ToCard(self.PCD_TRANSCEIVE,buf)
|
|
|
|
if not(status == self.MI_OK) or not(backLen == 4) or not((backData[0] & 0x0F) == 0x0A):
|
|
|
|
print "Error while writing"
|
|
|
|
if status == self.MI_OK:
|
|
|
|
print "Data writen"
|
2013-11-11 05:11:20 +00:00
|
|
|
|
|
|
|
|
|
|
|
def MFRC522_Init(self):
|
|
|
|
GPIO.output(self.NRSTPD, 1)
|
|
|
|
|
|
|
|
self.MFRC522_Reset();
|
|
|
|
|
|
|
|
|
|
|
|
self.Write_MFRC522(self.TModeReg, 0x8D)
|
|
|
|
self.Write_MFRC522(self.TPrescalerReg, 0x3E)
|
|
|
|
self.Write_MFRC522(self.TReloadRegL, 30)
|
|
|
|
self.Write_MFRC522(self.TReloadRegH, 0)
|
|
|
|
|
|
|
|
self.Write_MFRC522(self.TxAutoReg, 0x40)
|
|
|
|
self.Write_MFRC522(self.ModeReg, 0x3D)
|
|
|
|
self.AntennaOn()
|
|
|
|
|
|
|
|
continue_reading = True
|
|
|
|
# Capture SIGINT
|
|
|
|
def end_read(signal,frame):
|
|
|
|
global continue_reading
|
|
|
|
print "Ctrl+C captured, ending read."
|
|
|
|
continue_reading = False
|
|
|
|
|
|
|
|
signal.signal(signal.SIGINT, end_read)
|
|
|
|
|
|
|
|
MIFAREReader = MFRC522()
|
|
|
|
|
|
|
|
while continue_reading:
|
|
|
|
(status,TagType) = MIFAREReader.MFRC522_Request(MIFAREReader.PICC_REQIDL)
|
|
|
|
|
|
|
|
if status == MIFAREReader.MI_OK:
|
|
|
|
print "Card detected"
|
|
|
|
|
|
|
|
(status,backData) = MIFAREReader.MFRC522_Anticoll()
|
|
|
|
if status == MIFAREReader.MI_OK:
|
|
|
|
print "Card read UID: "+str(backData[0])+","+str(backData[1])+","+str(backData[2])+","+str(backData[3])+","+str(backData[4])
|
2013-11-11 07:12:06 +00:00
|
|
|
|
|
|
|
key = [0xFF,0xFF,0xFF,0xFF,0xFF,0xFF]
|
2013-11-11 05:11:20 +00:00
|
|
|
|
2013-11-11 07:12:06 +00:00
|
|
|
MIFAREReader.MFRC522_SelectTag(backData)
|
|
|
|
|
|
|
|
status = MIFAREReader.MFRC522_Auth(MIFAREReader.PICC_AUTHENT1A, 11, key, backData)
|
|
|
|
if status == MIFAREReader.MI_OK:
|
|
|
|
print "AUTH OK"
|
|
|
|
else:
|
|
|
|
print "AUTH ERROR"
|
2013-07-01 07:33:43 +00:00
|
|
|
|