5d52f4b51d
This change adds DWC3 QCOM USB phys and TCSR drivers. These are cherry-picked from the following LKML threads: *dwc3 qcom: https://lkml.org/lkml/2014/9/12/599 *tcsr: https://lkml.org/lkml/2015/2/9/579 We're also adding an additional patch to add the corresponding dev nodes in the IPQ806x and AP148 dts files. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45261
65 lines
1.5 KiB
Diff
65 lines
1.5 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -132,6 +132,7 @@
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gsbi2: gsbi@12480000 {
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compatible = "qcom,gsbi-v1.0.0";
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+ cell-index = <2>;
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reg = <0x12480000 0x100>;
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clocks = <&gcc GSBI2_H_CLK>;
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clock-names = "iface";
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@@ -140,6 +141,8 @@
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ranges;
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status = "disabled";
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+ syscon-tcsr = <&tcsr>;
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+
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uart2: serial@12490000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x12490000 0x1000>,
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@@ -167,6 +170,7 @@
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gsbi4: gsbi@16300000 {
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compatible = "qcom,gsbi-v1.0.0";
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+ cell-index = <4>;
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reg = <0x16300000 0x100>;
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clocks = <&gcc GSBI4_H_CLK>;
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clock-names = "iface";
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@@ -175,6 +179,8 @@
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ranges;
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status = "disabled";
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+ syscon-tcsr = <&tcsr>;
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+
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uart4: serial@16340000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x16340000 0x1000>,
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@@ -201,6 +207,7 @@
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gsbi5: gsbi@1a200000 {
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compatible = "qcom,gsbi-v1.0.0";
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+ cell-index = <5>;
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reg = <0x1a200000 0x100>;
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clocks = <&gcc GSBI5_H_CLK>;
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clock-names = "iface";
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@@ -209,6 +216,8 @@
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ranges;
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status = "disabled";
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+ syscon-tcsr = <&tcsr>;
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+
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uart5: serial@1a240000 {
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compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
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reg = <0x1a240000 0x1000>,
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@@ -279,6 +288,11 @@
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status = "disabled";
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};
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+ tcsr: syscon@1a400000 {
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+ compatible = "qcom,tcsr-ipq8064", "syscon";
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+ reg = <0x1a400000 0x100>;
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+ };
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+
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qcom,ssbi@500000 {
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compatible = "qcom,ssbi";
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reg = <0x00500000 0x1000>;
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