338 lines
8.1 KiB
C
338 lines
8.1 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2010
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* Thomas Langer, Ralph Hempel
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/addrspace.h>
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#include <asm/danube.h>
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#include <asm/reboot.h>
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#include <asm/io.h>
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extern ulong ifx_get_ddr_hz(void);
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extern ulong ifx_get_cpuclk(void);
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/* definitions for external PHYs / Switches */
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/* Split values into phy address and register address */
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#define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
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/* IDs and registers of known external switches */
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#define ID_SAMURAI_0 0x1020
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#define ID_SAMURAI_1 0x0007
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#define SAMURAI_ID_REG0 0xA0
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#define SAMURAI_ID_REG1 0xA1
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#define ID_TANTOS 0x2599
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void _machine_restart(void)
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{
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*DANUBE_RCU_RST_REQ |=1<<30;
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}
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#ifdef CONFIG_SYS_RAMBOOT
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phys_size_t initdram(int board_type)
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{
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return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM);
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}
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#elif defined(CONFIG_USE_DDR_RAM)
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phys_size_t initdram(int board_type)
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{
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return (CONFIG_SYS_MAX_RAM);
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}
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#else
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static ulong max_sdram_size(void) /* per Chip Select */
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{
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/* The only supported SDRAM data width is 16bit.
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*/
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#define CFG_DW 4
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/* The only supported number of SDRAM banks is 4.
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*/
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#define CFG_NB 4
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ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0;
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int cols = cfgpb0 & 0xF;
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int rows = (cfgpb0 & 0xF0) >> 4;
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ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB;
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return size;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'.
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*/
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static long int dram_size(long int *base, long int maxsize)
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{
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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phys_size_t initdram(int board_type)
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{
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int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0;
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ulong size, max_size = 0;
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ulong our_address;
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/* load t9 into our_address */
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asm volatile ("move %0, $25" : "=r" (our_address) :);
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/* Can't probe for RAM size unless we are running from Flash.
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* find out whether running from DRAM or Flash.
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*/
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if (CPHYSADDR(our_address) < CPHYSADDR(PHYS_FLASH_1))
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{
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return max_sdram_size();
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}
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for (cols = 0x8; cols <= 0xC; cols++)
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{
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for (rows = 0xB; rows <= 0xD; rows++)
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{
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*DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) |
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(rows << 4) | cols;
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size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
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max_sdram_size());
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if (size > max_size)
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{
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best_val = *DANUBE_SDRAM_MC_CFGPB0;
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max_size = size;
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}
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}
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}
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*DANUBE_SDRAM_MC_CFGPB0 = best_val;
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return max_size;
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}
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#endif
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int checkboard (void)
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{
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unsigned long chipid = *DANUBE_MPS_CHIPID;
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int part_num;
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puts ("Board: ");
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part_num = DANUBE_MPS_CHIPID_PARTNUM_GET(chipid);
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switch (part_num)
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{
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case 0x129:
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case 0x12D:
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puts("Danube/Twinpass/Vinax-VE ");
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break;
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default:
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printf ("unknown, chip part number 0x%03X ", part_num);
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break;
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}
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printf ("V1.%ld, ", DANUBE_MPS_CHIPID_VERSION_GET(chipid));
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printf("DDR Speed %ld MHz, ", ifx_get_ddr_hz()/1000000);
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printf("CPU Speed %ld MHz\n", ifx_get_cpuclk()/1000000);
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return 0;
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}
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#ifdef CONFIG_SKIP_LOWLEVEL_INIT
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int board_early_init_f(void)
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{
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#ifdef CONFIG_EBU_ADDSEL0
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(*DANUBE_EBU_ADDSEL0) = CONFIG_EBU_ADDSEL0;
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#endif
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#ifdef CONFIG_EBU_ADDSEL1
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(*DANUBE_EBU_ADDSEL1) = CONFIG_EBU_ADDSEL1;
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#endif
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#ifdef CONFIG_EBU_ADDSEL2
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(*DANUBE_EBU_ADDSEL2) = CONFIG_EBU_ADDSEL2;
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#endif
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#ifdef CONFIG_EBU_ADDSEL3
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(*DANUBE_EBU_ADDSEL3) = CONFIG_EBU_ADDSEL3;
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#endif
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#ifdef CONFIG_EBU_BUSCON0
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(*DANUBE_EBU_BUSCON0) = CONFIG_EBU_BUSCON0;
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#endif
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#ifdef CONFIG_EBU_BUSCON1
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(*DANUBE_EBU_BUSCON1) = CONFIG_EBU_BUSCON1;
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#endif
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#ifdef CONFIG_EBU_BUSCON2
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(*DANUBE_EBU_BUSCON2) = CONFIG_EBU_BUSCON2;
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#endif
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#ifdef CONFIG_EBU_BUSCON3
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(*DANUBE_EBU_BUSCON3) = CONFIG_EBU_BUSCON3;
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#endif
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return 0;
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}
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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#ifdef CONFIG_EXTRA_SWITCH
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static int external_switch_init(void)
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{
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unsigned short chipid0=0xdead, chipid1=0xbeef;
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static char * const name = "lq_cpe_eth";
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#ifdef CLK_OUT2_25MHZ
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*DANUBE_GPIO_P0_DIR=0x0000ae78;
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*DANUBE_GPIO_P0_ALTSEL0=0x00008078;
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//joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080;
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*DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1
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*DANUBE_CGU_IFCCR=0x00400010;
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*DANUBE_GPIO_P0_OD=0x0000ae78;
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#endif
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/* earlier no valid response is available, at least on Twinpass & Tantos @ 111MHz, M4530 platform */
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udelay(100000);
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debug("\nsearching for Samurai switch ... ");
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if ( (miiphy_read(name, PHYADDR(SAMURAI_ID_REG0), &chipid0)==0) &&
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(miiphy_read(name, PHYADDR(SAMURAI_ID_REG1), &chipid1)==0) ) {
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if (((chipid0 & 0xFFF0) == ID_SAMURAI_0) &&
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((chipid1 & 0x000F) == ID_SAMURAI_1)) {
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debug("found");
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/* enable "Crossover Auto Detect" + defaults */
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/* P0 */
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miiphy_write(name, PHYADDR(0x01), 0x840F);
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/* P1 */
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miiphy_write(name, PHYADDR(0x03), 0x840F);
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/* P2 */
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miiphy_write(name, PHYADDR(0x05), 0x840F);
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/* P3 */
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miiphy_write(name, PHYADDR(0x07), 0x840F);
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/* P4 */
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miiphy_write(name, PHYADDR(0x08), 0x840F);
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/* P5 */
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miiphy_write(name, PHYADDR(0x09), 0x840F);
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/* System Control 4: CPU on port 1 and other */
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miiphy_write(name, PHYADDR(0x12), 0x3602);
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#ifdef CLK_OUT2_25MHZ
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/* Bandwidth Control Enable Register: enable */
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miiphy_write(name, PHYADDR(0x33), 0x4000);
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#endif
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}
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}
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debug("\nsearching for TANTOS switch ... ");
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if (miiphy_read(name, PHYADDR(0x101), &chipid0) == 0) {
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if (chipid0 == ID_TANTOS) {
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debug("found");
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/* P5 Basic Control: Force Link Up */
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miiphy_write(name, PHYADDR(0xA1), 0x0004);
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/* P6 Basic Control: Force Link Up */
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miiphy_write(name, PHYADDR(0xC1), 0x0004);
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/* RGMII/MII Port Control (P4/5/6) */
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miiphy_write(name, PHYADDR(0xF5), 0x0773);
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/* Software workaround. */
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/* PHY reset from P0 to P4. */
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/* set data for indirect write */
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miiphy_write(name, PHYADDR(0x121), 0x8000);
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/* P0 */
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miiphy_write(name, PHYADDR(0x120), 0x0400);
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udelay(1000);
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/* P1 */
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miiphy_write(name, PHYADDR(0x120), 0x0420);
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udelay(1000);
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/* P2 */
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miiphy_write(name, PHYADDR(0x120), 0x0440);
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udelay(1000);
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/* P3 */
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miiphy_write(name, PHYADDR(0x120), 0x0460);
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udelay(1000);
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/* P4 */
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miiphy_write(name, PHYADDR(0x120), 0x0480);
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udelay(1000);
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}
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}
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debug("\n");
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return 0;
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}
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#endif /* CONFIG_EXTRA_SWITCH */
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int board_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_IFX_ETOP)
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*DANUBE_PMU_PWDCR &= 0xFFFFEFDF;
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*DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/
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if (lq_eth_initialize(bis)<0)
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return -1;
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*DANUBE_RCU_RST_REQ |=1;
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udelay(200000);
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*DANUBE_RCU_RST_REQ &=(unsigned long)~1;
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udelay(1000);
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#ifdef CONFIG_EXTRA_SWITCH
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if (external_switch_init()<0)
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return -1;
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#endif /* CONFIG_EXTRA_SWITCH */
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#endif /* CONFIG_IFX_ETOP */
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return 0;
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}
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