2b1c6b21b5
As usual these patches were extracted and rebased from the raspberry pi repo: https://github.com/raspberrypi/linux/tree/rpi-4.4.y Also adds support for Raspberry Pi Compute Module 3 (untested). Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
114 lines
3.7 KiB
Diff
114 lines
3.7 KiB
Diff
From 350247e0611f171a3372386e389e24746daff84f Mon Sep 17 00:00:00 2001
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From: Martin Sperl <kernel@martin.sperl.org>
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Date: Wed, 16 Mar 2016 12:25:00 -0700
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Subject: [PATCH] dmaengine: bcm2835: limit max length based on channel type
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The bcm2835 dma system has 2 basic types of dma-channels:
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* "normal" channels
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* "light" channels
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Lite channels are limited in several aspects:
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* internal data-structure is 128 bit (not 256)
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* does not support BCM2835_DMA_TDMODE (2D)
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* DMA length register is limited to 16 bit.
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so 0-65535 (not 0-65536 as mentioned in the official datasheet)
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* BCM2835_DMA_S/D_IGNORE are not supported
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The detection of the type of mode is implemented by looking at
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the LITE bit in the DEBUG register for each channel.
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This allows automatic detection.
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Based on this the maximum block size is set to (64K - 4) or to 1G
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and this limit is honored during generation of control block
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chains. The effect is that when a LITE channel is used more
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control blocks are used to do the same transfer (compared
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to a normal channel).
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As there are several sources/target DREQS that are 32 bit wide
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we need to have the transfer to be a multiple of 4 as this would
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break the transfer otherwise.
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This is why the limit of (64K - 4) was chosen over the
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alternative of (64K - 4K).
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Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
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Reviewed-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Eric Anholt <eric@anholt.net>
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Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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---
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drivers/dma/bcm2835-dma.c | 29 ++++++++++++++++++++++++++---
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1 file changed, 26 insertions(+), 3 deletions(-)
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--- a/drivers/dma/bcm2835-dma.c
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+++ b/drivers/dma/bcm2835-dma.c
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@@ -81,6 +81,8 @@ struct bcm2835_chan {
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void __iomem *chan_base;
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int irq_number;
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+
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+ bool is_lite_channel;
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};
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struct bcm2835_desc {
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@@ -169,6 +171,16 @@ struct bcm2835_desc {
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#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
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#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
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+/* the max dma length for different channels */
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+#define MAX_DMA_LEN SZ_1G
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+#define MAX_LITE_DMA_LEN (SZ_64K - 4)
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+
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+static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
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+{
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+ /* lite and normal channels have different max frame length */
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+ return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN;
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+}
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+
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/* how many frames of max_len size do we need to transfer len bytes */
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static inline size_t bcm2835_dma_frames_for_length(size_t len,
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size_t max_len)
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@@ -217,8 +229,10 @@ static void bcm2835_dma_create_cb_set_le
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size_t *total_len,
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u32 finalextrainfo)
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{
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- /* set the length */
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- control_block->length = len;
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+ size_t max_len = bcm2835_dma_max_frame_length(chan);
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+
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+ /* set the length taking lite-channel limitations into account */
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+ control_block->length = min_t(u32, len, max_len);
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/* finished if we have no period_length */
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if (!period_len)
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@@ -544,6 +558,7 @@ static struct dma_async_tx_descriptor *b
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dma_addr_t src, dst;
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u32 info = BCM2835_DMA_WAIT_RESP;
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u32 extra = BCM2835_DMA_INT_EN;
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+ size_t max_len = bcm2835_dma_max_frame_length(c);
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size_t frames;
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/* Grab configuration */
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@@ -586,7 +601,10 @@ static struct dma_async_tx_descriptor *b
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}
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/* calculate number of frames */
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- frames = DIV_ROUND_UP(buf_len, period_len);
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+ frames = /* number of periods */
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+ DIV_ROUND_UP(buf_len, period_len) *
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+ /* number of frames per period */
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+ bcm2835_dma_frames_for_length(period_len, max_len);
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/*
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* allocate the CB chain
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@@ -685,6 +703,11 @@ static int bcm2835_dma_chan_init(struct
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c->ch = chan_id;
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c->irq_number = irq;
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+ /* check in DEBUG register if this is a LITE channel */
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+ if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
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+ BCM2835_DMA_DEBUG_LITE)
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+ c->is_lite_channel = true;
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+
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return 0;
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}
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