f9b8328d79
Add the ranges property to the PCI bridges where missing. Add the unit address to PCI bridge where missing. Rework the complete rt3883 pci node. Drop the PCI unit nodes from the dtsi. They are not used by any dts file and should be rather in the dts than in the SoC dtsi. Express the PCI-PCI bridge in a clean devicetree syntax. The ralink,pci-slot isn't used by any driver, drop it. Move the pci interrupt controller out of the pci node. It doesn't share the same reg and therefore should be an independent/SoC child node. Move the pci related rt3883 pinctrl setting to the dtsi instead of defining the very same for each rt3883 board. If the device_type property is used for PCI units, the unit is treated as pci bridge which it isn't. Drop it for PCI units. Reference pci-bridges or the pci node defined in the dtsi instead of recreating the whole node hierarchy. It allows to change the referenced node in the dtsi without the need to touch all dts. Fix the PCI(e) wireless unit addresses. All our PCI(e) wireless chips are the first device on the bus. The unit address has to be the bus address instead of the PCI vendor/device id. Signed-off-by: Mathias Kresin <dev@kresin.me>
197 lines
2.9 KiB
Text
197 lines
2.9 KiB
Text
/dts-v1/;
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "tplink,mr200", "ralink,mt7620a-soc";
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model = "TP-Link Archer MR200";
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aliases {
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led-status = &led_power;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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gpio-leds {
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compatible = "gpio-leds";
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lan {
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label = "mr200:white:lan";
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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};
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wan {
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label = "mr200:white:wan";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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};
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led_power: power {
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label = "mr200:white:power";
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gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
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};
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4g {
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label = "mr200:white:4g";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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wps {
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label = "mr200:white:wps";
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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signal1 {
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label = "mr200:white:signal1";
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gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
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};
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signal2 {
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label = "mr200:white:signal2";
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gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
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};
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signal3 {
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label = "mr200:white:signal3";
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gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
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};
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signal4 {
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label = "mr200:white:signal4";
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gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
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};
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wlan {
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label = "mr200:white:wlan";
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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#address-cells = <1>;
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#size-cells = <0>;
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reset {
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label = "reset";
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gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_RESTART>;
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};
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rfkill {
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label = "rfkill";
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gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
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linux,code = <KEY_RFKILL>;
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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power_usb {
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gpio-export,name = "power_usb1";
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gpio-export,output = <1>;
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gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x20000>;
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read-only;
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};
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partition@20000 {
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label = "firmware";
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reg = <0x20000 0x7b0000>;
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};
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rom: partition@7d0000 {
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label = "rom";
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reg = <0x7d0000 0x10000>;
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read-only;
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};
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partition@7e0000 {
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label = "romfile";
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reg = <0x7e0000 0x10000>;
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read-only;
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};
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radio: partition@7f0000 {
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label = "radio";
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reg = <0x7f0000 0x10000>;
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read-only;
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};
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd", "ephy", "spi refclk";
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ralink,function = "gpio";
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};
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};
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};
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ðernet {
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mtd-mac-address = <&rom 0xf100>;
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mediatek,portmap = "llll";
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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&gsw {
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mediatek,port4 = "ephy";
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};
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&wmac {
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ralink,mtd-eeprom = <&radio 0>;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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mediatek,mtd-eeprom = <&radio 32768>;
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};
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};
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