5a6229a93d
Mediatek has a reference platform that pairs an MT7620A with an MT7530W, where the latter responds on MDIO address 0x1f while both chips respond on 0x0 to 0x4. The driver special-cases this arrangement to make sure it's talking to the right chip, but two different ways in two different places. This patch consolidates the detection without the current requirement of both tests to be separately satisfied in the DTS. Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
214 lines
3.5 KiB
Text
214 lines
3.5 KiB
Text
/*
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* Device Tree file for the Edimax BR-6478AC V2
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* based on Linksys E1700
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*
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* Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
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* Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
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* Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/include/ "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
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model = "Edimax BR-6478AC v2";
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aliases {
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led-status = &led_power;
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};
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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reset_wps {
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label = "reset_wps";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "br-6478ac-v2:white:power";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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};
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wan {
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label = "br-6478ac-v2:blue:wan";
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gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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};
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wlan {
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label = "br-6478ac-v2:blue:wlan";
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gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
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};
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usb {
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label = "br-6478ac-v2:blue:usb";
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gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
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};
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};
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gpio_export {
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compatible = "gpio-export";
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#size-cells = <0>;
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usb-power {
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gpio-export,name="usb-power";
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gpio-export,output=<1>;
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gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* pin45 */
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};
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};
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};
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&gpio2 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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m25p80@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0 0>;
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linux,modalias = "m25p80", "mx25l6405d";
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spi-max-frequency = <10000000>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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read-only;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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partition@50000 {
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label = "cimage";
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reg = <0x50000 0x20000>;
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read-only;
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};
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partition@70000 {
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label = "firmware";
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reg = <0x00070000 0x00790000>;
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};
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "i2c", "uartf", "wdt", "pa",
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"ephy", "nd_sd", "wled";
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ralink,function = "gpio";
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};
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};
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};
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ðernet {
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status = "okay";
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mtd-mac-address = <&factory 0x4>;
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
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mediatek,portmap = "wllll";
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port@5 {
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status = "okay";
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mediatek,fixed-link = <1000 1 1 1>;
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phy-mode = "rgmii";
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};
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mdio-bus {
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status = "okay";
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phy0: ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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};
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phy1: ethernet-phy@1 {
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reg = <1>;
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phy-mode = "rgmii";
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};
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phy2: ethernet-phy@2 {
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reg = <2>;
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phy-mode = "rgmii";
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};
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phy3: ethernet-phy@3 {
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reg = <3>;
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phy-mode = "rgmii";
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};
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phy4: ethernet-phy@4 {
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reg = <4>;
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phy-mode = "rgmii";
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};
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phy1f: ethernet-phy@1f {
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reg = <0x1f>;
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phy-mode = "rgmii";
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};
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};
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};
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&gsw {
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mediatek,port4 = "gmac";
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};
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&wmac {
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ralink,mtd-eeprom = <&factory 0>;
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};
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&pcie {
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status = "okay";
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pcie-bridge {
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mt76@0,0 {
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reg = <0x0000 0 0 0 0>;
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device_type = "pci";
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mediatek,mtd-eeprom = <&factory 0x8000>;
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mediatek,2ghz = <0>;
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};
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};
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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