c9ae111a20
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.12, and Linux v3.13. This work mainly covers: * Finishes work for sharing the pxa nand driver(drivers/mtd/nand/pxa3xx_nand.c) between the PXA family, and the Armada family. * timer initialization update, and access function for the Armada family. * Generic IRQ handling backporting. * Some bug fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39566
180 lines
6.8 KiB
Diff
180 lines
6.8 KiB
Diff
From 9c2caf4d2d60780182d7754896c41496192b99c2 Mon Sep 17 00:00:00 2001
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From: Arnaud Ebalard <arno@natisbad.org>
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Date: Tue, 5 Nov 2013 21:46:02 +0100
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Subject: [PATCH 203/203] ARM: mvebu: fix second and third PCIe unit of Armada
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XP mv78260
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mv78260 flavour of Marvell Armada XP SoC has 3 PCIe units. The
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two first units are both x4 and quad x1 capable. The third unit
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is only x4 capable. This patch fixes mv78260 .dtsi to reflect
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those capabilities.
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Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
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Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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Cc: <stable@vger.kernel.org> # v3.10.x
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Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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---
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arch/arm/boot/dts/armada-xp-mv78260.dtsi | 109 ++++++++++++++++++++++++-------
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1 file changed, 85 insertions(+), 24 deletions(-)
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--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
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+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
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@@ -48,7 +48,7 @@
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/*
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* MV78260 has 3 PCIe units Gen2.0: Two units can be
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* configured as x4 or quad x1 lanes. One unit is
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- * x4/x1.
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+ * x4 only.
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*/
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pcie-controller {
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compatible = "marvell,armada-xp-pcie";
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@@ -68,7 +68,9 @@
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
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0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
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0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
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- 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
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+ 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
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+ 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
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+ 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
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0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
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@@ -77,10 +79,18 @@
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0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
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- 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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- 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
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- 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
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- 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
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+
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+ 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
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+ 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
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+ 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
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+ 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
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+ 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
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+ 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
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+ 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
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+ 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
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+
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+ 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
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+ 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
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pcie@1,0 {
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device_type = "pci";
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@@ -106,8 +116,8 @@
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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- ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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- 0x81000000 0 0 0x81000000 0x2 0 1 0>;
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+ ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
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+ 0x81000000 0 0 0x81000000 0x2 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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@@ -150,37 +160,88 @@
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status = "disabled";
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};
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- pcie@9,0 {
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+ pcie@5,0 {
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device_type = "pci";
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- assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
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- reg = <0x4800 0 0 0 0>;
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+ assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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+ reg = <0x2800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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- ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
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- 0x81000000 0 0 0x81000000 0x9 0 1 0>;
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+ ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
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+ 0x81000000 0 0 0x81000000 0x5 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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- interrupt-map = <0 0 0 0 &mpic 99>;
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- marvell,pcie-port = <2>;
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+ interrupt-map = <0 0 0 0 &mpic 62>;
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+ marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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- clocks = <&gateclk 26>;
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+ clocks = <&gateclk 9>;
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status = "disabled";
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};
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- pcie@10,0 {
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+ pcie@6,0 {
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device_type = "pci";
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- assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
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- reg = <0x5000 0 0 0 0>;
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+ assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
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+ reg = <0x3000 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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- ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
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- 0x81000000 0 0 0x81000000 0xa 0 1 0>;
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+ ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
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+ 0x81000000 0 0 0x81000000 0x6 0 1 0>;
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interrupt-map-mask = <0 0 0 0>;
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- interrupt-map = <0 0 0 0 &mpic 103>;
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- marvell,pcie-port = <3>;
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+ interrupt-map = <0 0 0 0 &mpic 63>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <1>;
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+ clocks = <&gateclk 10>;
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+ status = "disabled";
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+ };
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+
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+ pcie@7,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
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+ reg = <0x3800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
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+ 0x81000000 0 0 0x81000000 0x7 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 64>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <2>;
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+ clocks = <&gateclk 11>;
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+ status = "disabled";
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+ };
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+
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+ pcie@8,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
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+ reg = <0x4000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
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+ 0x81000000 0 0 0x81000000 0x8 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 65>;
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+ marvell,pcie-port = <1>;
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+ marvell,pcie-lane = <3>;
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+ clocks = <&gateclk 12>;
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+ status = "disabled";
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+ };
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+
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+ pcie@9,0 {
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+ device_type = "pci";
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+ assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
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+ reg = <0x4800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
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+ 0x81000000 0 0 0x81000000 0x9 0 1 0>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &mpic 99>;
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+ marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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- clocks = <&gateclk 27>;
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+ clocks = <&gateclk 26>;
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status = "disabled";
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};
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};
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