bb255f7429
Signed-off-by: John Crispin <john@phrozen.org>
488 lines
14 KiB
Diff
488 lines
14 KiB
Diff
From e8d6fd46f5f3c5860fa7fa98004de9bd97c0d869 Mon Sep 17 00:00:00 2001
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From: Senthilkumar N L <snlakshm@codeaurora.org>
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Date: Tue, 6 Jan 2015 12:52:23 +0530
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Subject: [PATCH 34/37] qcom: ipq4019: Add IPQ4019 USB HS/SS PHY drivers
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These drivers handles control and configuration of the HS
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and SS USB PHY transceivers.
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Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
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---
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drivers/usb/phy/Kconfig | 11 ++
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drivers/usb/phy/Makefile | 2 +
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drivers/usb/phy/phy-qca-baldur.c | 262 ++++++++++++++++++++++++++++++++++++++
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drivers/usb/phy/phy-qca-uniphy.c | 171 +++++++++++++++++++++++++
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4 files changed, 446 insertions(+)
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create mode 100644 drivers/usb/phy/phy-qca-baldur.c
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create mode 100644 drivers/usb/phy/phy-qca-uniphy.c
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--- a/drivers/usb/phy/Kconfig
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+++ b/drivers/usb/phy/Kconfig
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@@ -194,6 +194,17 @@ config USB_MXS_PHY
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MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
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+config USB_IPQ4019_PHY
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+ tristate "IPQ4019 PHY wrappers support"
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+ depends on (USB || USB_GADGET) && ARCH_QCOM
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+ select USB_PHY
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+ help
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+ Enable this to support the USB PHY transceivers on QCA961x chips.
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+ It handles PHY initialization, clock management required after
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+ resetting the hardware and power management.
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+ This driver is required even for peripheral only or host only
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+ mode configurations.
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+
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config USB_ULPI
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bool "Generic ULPI Transceiver Driver"
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depends on ARM || ARM64
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--- a/drivers/usb/phy/Makefile
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+++ b/drivers/usb/phy/Makefile
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@@ -21,6 +21,8 @@ obj-$(CONFIG_USB_GPIO_VBUS) += phy-gpio
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obj-$(CONFIG_USB_ISP1301) += phy-isp1301.o
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obj-$(CONFIG_USB_MSM_OTG) += phy-msm-usb.o
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obj-$(CONFIG_USB_QCOM_8X16_PHY) += phy-qcom-8x16-usb.o
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+obj-$(CONFIG_USB_IPQ4019_PHY) += phy-qca-baldur.o
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+obj-$(CONFIG_USB_IPQ4019_PHY) += phy-qca-uniphy.o
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obj-$(CONFIG_USB_MV_OTG) += phy-mv-usb.o
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obj-$(CONFIG_USB_MXS_PHY) += phy-mxs-usb.o
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obj-$(CONFIG_USB_ULPI) += phy-ulpi.o
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--- /dev/null
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+++ b/drivers/usb/phy/phy-qca-baldur.c
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@@ -0,0 +1,262 @@
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+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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+ *
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+ * Permission to use, copy, modify, and/or distribute this software for any
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+ * purpose with or without fee is hereby granted, provided that the above
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+ * copyright notice and this permission notice appear in all copies.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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+ *
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/usb/phy.h>
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+#include <linux/reset.h>
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+#include <linux/of_device.h>
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+
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+/**
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+ * USB Hardware registers
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+ */
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+#define PHY_CTRL0_ADDR 0x000
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+#define PHY_CTRL1_ADDR 0x004
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+#define PHY_CTRL2_ADDR 0x008
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+#define PHY_CTRL3_ADDR 0x00C
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+#define PHY_CTRL4_ADDR 0x010
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+#define PHY_MISC_ADDR 0x024
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+#define PHY_IPG_ADDR 0x030
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+
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+#define PHY_CTRL0_EMU_ADDR 0x180
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+#define PHY_CTRL1_EMU_ADDR 0x184
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+#define PHY_CTRL2_EMU_ADDR 0x188
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+#define PHY_CTRL3_EMU_ADDR 0x18C
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+#define PHY_CTRL4_EMU_ADDR 0x190
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+#define PHY_MISC_EMU_ADDR 0x1A4
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+#define PHY_IPG_EMU_ADDR 0x1B0
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+
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+#define PHY_CTRL0_VAL 0xA4600015
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+#define PHY_CTRL1_VAL 0x09500000
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+#define PHY_CTRL2_VAL 0x00058180
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+#define PHY_CTRL3_VAL 0x6DB6DCD6
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+#define PHY_CTRL4_VAL 0x836DB6DB
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+#define PHY_MISC_VAL 0x3803FB0C
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+#define PHY_IPG_VAL 0x47323232
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+
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+#define PHY_CTRL0_EMU_VAL 0xb4000015
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+#define PHY_CTRL1_EMU_VAL 0x09500000
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+#define PHY_CTRL2_EMU_VAL 0x00058180
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+#define PHY_CTRL3_EMU_VAL 0x6DB6DCD6
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+#define PHY_CTRL4_EMU_VAL 0x836DB6DB
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+#define PHY_MISC_EMU_VAL 0x3803FB0C
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+#define PHY_IPG_EMU_VAL 0x47323232
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+
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+#define USB30_HS_PHY_HOST_MODE (0x01 << 21)
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+#define USB20_HS_PHY_HOST_MODE (0x01 << 5)
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+
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+/* used to differentiate between USB3 HS and USB2 HS PHY */
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+struct qca_baldur_hs_data {
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+ unsigned int usb3_hs_phy;
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+ unsigned int phy_config_offset;
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+};
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+
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+struct qca_baldur_hs_phy {
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+ struct device *dev;
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+ struct usb_phy phy;
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+
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+ void __iomem *base;
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+ void __iomem *qscratch_base;
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+
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+ struct reset_control *por_rst;
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+ struct reset_control *srif_rst;
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+
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+ unsigned int host;
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+ unsigned int emulation;
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+ const struct qca_baldur_hs_data *data;
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+};
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+
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+#define phy_to_dw_phy(x) container_of((x), struct qca_baldur_hs_phy, phy)
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+
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+static int qca_baldur_phy_read(struct usb_phy *x, u32 reg)
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+{
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+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
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+
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+ return readl(phy->base + reg);
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+}
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+
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+static int qca_baldur_phy_write(struct usb_phy *x, u32 val, u32 reg)
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+{
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+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
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+
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+ writel(val, phy->base + reg);
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+ return 0;
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+}
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+
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+static int qca_baldur_hs_phy_init(struct usb_phy *x)
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+{
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+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
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+
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+ /* assert HS PHY POR reset */
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+ reset_control_assert(phy->por_rst);
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+ msleep(10);
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+
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+ /* assert HS PHY SRIF reset */
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+ reset_control_assert(phy->srif_rst);
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+ msleep(10);
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+
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+ /* deassert HS PHY SRIF reset and program HS PHY registers */
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+ reset_control_deassert(phy->srif_rst);
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+ msleep(10);
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+
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+ if (!phy->emulation) {
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+ /* perform PHY register writes */
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+ writel(PHY_CTRL0_VAL, phy->base + PHY_CTRL0_ADDR);
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+ writel(PHY_CTRL1_VAL, phy->base + PHY_CTRL1_ADDR);
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+ writel(PHY_CTRL2_VAL, phy->base + PHY_CTRL2_ADDR);
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+ writel(PHY_CTRL3_VAL, phy->base + PHY_CTRL3_ADDR);
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+ writel(PHY_CTRL4_VAL, phy->base + PHY_CTRL4_ADDR);
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+ writel(PHY_MISC_VAL, phy->base + PHY_MISC_ADDR);
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+ writel(PHY_IPG_VAL, phy->base + PHY_IPG_ADDR);
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+ } else {
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+ /* perform PHY register writes */
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+ writel(PHY_CTRL0_EMU_VAL, phy->base + PHY_CTRL0_EMU_ADDR);
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+ writel(PHY_CTRL1_EMU_VAL, phy->base + PHY_CTRL1_EMU_ADDR);
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+ writel(PHY_CTRL2_EMU_VAL, phy->base + PHY_CTRL2_EMU_ADDR);
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+ writel(PHY_CTRL3_EMU_VAL, phy->base + PHY_CTRL3_EMU_ADDR);
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+ writel(PHY_CTRL4_EMU_VAL, phy->base + PHY_CTRL4_EMU_ADDR);
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+ writel(PHY_MISC_EMU_VAL, phy->base + PHY_MISC_EMU_ADDR);
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+ writel(PHY_IPG_EMU_VAL, phy->base + PHY_IPG_EMU_ADDR);
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+ }
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+
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+ msleep(10);
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+
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+ /* de-assert USB3 HS PHY POR reset */
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+ reset_control_deassert(phy->por_rst);
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+
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+ return 0;
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+}
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+
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+static int qca_baldur_hs_get_resources(struct qca_baldur_hs_phy *phy)
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+{
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+ struct platform_device *pdev = to_platform_device(phy->dev);
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+ struct resource *res;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ phy->base = devm_ioremap_resource(phy->dev, res);
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+ if (IS_ERR(phy->base))
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+ return PTR_ERR(phy->base);
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+
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+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
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+ if (IS_ERR(phy->por_rst))
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+ return PTR_ERR(phy->por_rst);
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+
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+ phy->srif_rst = devm_reset_control_get(phy->dev, "srif_rst");
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+ if (IS_ERR(phy->srif_rst))
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+ return PTR_ERR(phy->srif_rst);
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+
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+ return 0;
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+}
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+
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+static void qca_baldur_hs_put_resources(struct qca_baldur_hs_phy *phy)
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+{
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+ reset_control_assert(phy->srif_rst);
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+ reset_control_assert(phy->por_rst);
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+}
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+
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+static int qca_baldur_hs_remove(struct platform_device *pdev)
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+{
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+ struct qca_baldur_hs_phy *phy = platform_get_drvdata(pdev);
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+
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+ usb_remove_phy(&phy->phy);
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+ return 0;
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+}
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+
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+static void qca_baldur_hs_phy_shutdown(struct usb_phy *x)
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+{
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+ struct qca_baldur_hs_phy *phy = phy_to_dw_phy(x);
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+
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+ qca_baldur_hs_put_resources(phy);
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+}
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+
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+static struct usb_phy_io_ops qca_baldur_io_ops = {
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+ .read = qca_baldur_phy_read,
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+ .write = qca_baldur_phy_write,
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+};
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+
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+static const struct qca_baldur_hs_data usb3_hs_data = {
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+ .usb3_hs_phy = 1,
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+ .phy_config_offset = USB30_HS_PHY_HOST_MODE,
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+};
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+
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+static const struct qca_baldur_hs_data usb2_hs_data = {
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+ .usb3_hs_phy = 0,
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+ .phy_config_offset = USB20_HS_PHY_HOST_MODE,
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+};
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+
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+static const struct of_device_id qca_baldur_hs_id_table[] = {
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+ { .compatible = "qca,baldur-usb3-hsphy", .data = &usb3_hs_data },
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+ { .compatible = "qca,baldur-usb2-hsphy", .data = &usb2_hs_data },
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+ { /* Sentinel */ }
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+};
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+MODULE_DEVICE_TABLE(of, qca_baldur_hs_id_table);
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+
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+static int qca_baldur_hs_probe(struct platform_device *pdev)
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+{
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+ const struct of_device_id *match;
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+ struct qca_baldur_hs_phy *phy;
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+ int err;
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+
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+ match = of_match_device(qca_baldur_hs_id_table, &pdev->dev);
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+ if (!match)
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+ return -ENODEV;
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+
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+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
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+ if (!phy)
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+ return -ENOMEM;
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+
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+ platform_set_drvdata(pdev, phy);
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+ phy->dev = &pdev->dev;
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+
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+ phy->data = match->data;
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+
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+ err = qca_baldur_hs_get_resources(phy);
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+ if (err < 0) {
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+ dev_err(&pdev->dev, "failed to request resources: %d\n", err);
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+ return err;
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+ }
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+
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+ phy->phy.dev = phy->dev;
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+ phy->phy.label = "qca-baldur-hsphy";
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+ phy->phy.init = qca_baldur_hs_phy_init;
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+ phy->phy.shutdown = qca_baldur_hs_phy_shutdown;
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+ phy->phy.type = USB_PHY_TYPE_USB2;
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+ phy->phy.io_ops = &qca_baldur_io_ops;
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+
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+ err = usb_add_phy_dev(&phy->phy);
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+ return err;
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+}
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+
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+static struct platform_driver qca_baldur_hs_driver = {
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+ .probe = qca_baldur_hs_probe,
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+ .remove = qca_baldur_hs_remove,
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+ .driver = {
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+ .name = "qca-baldur-hsphy",
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+ .owner = THIS_MODULE,
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+ .of_match_table = qca_baldur_hs_id_table,
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+ },
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+};
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+
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+module_platform_driver(qca_baldur_hs_driver);
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+
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+MODULE_ALIAS("platform:qca-baldur-hsphy");
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+MODULE_LICENSE("Dual BSD/GPL");
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+MODULE_DESCRIPTION("USB3 QCA BALDUR HSPHY driver");
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--- /dev/null
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+++ b/drivers/usb/phy/phy-qca-uniphy.c
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@@ -0,0 +1,171 @@
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+/* Copyright (c) 2015, The Linux Foundation. All rights reserved.
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+ *
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+ * Permission to use, copy, modify, and/or distribute this software for any
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+ * purpose with or without fee is hereby granted, provided that the above
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+ * copyright notice and this permission notice appear in all copies.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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+ *
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+ */
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+
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/regulator/consumer.h>
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+#include <linux/usb/phy.h>
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+#include <linux/reset.h>
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+#include <linux/of_device.h>
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+
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+struct qca_uni_ss_phy {
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+ struct usb_phy phy;
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+ struct device *dev;
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+
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+ void __iomem *base;
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+
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+ struct reset_control *por_rst;
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+
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+ unsigned int host;
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+};
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+
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+#define phy_to_dw_phy(x) container_of((x), struct qca_uni_ss_phy, phy)
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+
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+/**
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+ * Write register
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+ *
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+ * @base - PHY base virtual address.
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+ * @offset - register offset.
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+ */
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+static u32 qca_uni_ss_read(void __iomem *base, u32 offset)
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+{
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+ u32 value;
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+ value = readl_relaxed(base + offset);
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+ return value;
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+}
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+
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+/**
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+ * Write register
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+ *
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+ * @base - PHY base virtual address.
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+ * @offset - register offset.
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+ * @val - value to write.
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+ */
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+static void qca_uni_ss_write(void __iomem *base, u32 offset, u32 val)
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+{
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+ writel(val, base + offset);
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+ udelay(100);
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+}
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+
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+static void qca_uni_ss_phy_shutdown(struct usb_phy *x)
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+{
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+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
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+
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+ /* assert SS PHY POR reset */
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+ reset_control_assert(phy->por_rst);
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+}
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+
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+static int qca_uni_ss_phy_init(struct usb_phy *x)
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+{
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+ struct qca_uni_ss_phy *phy = phy_to_dw_phy(x);
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+
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+ /* assert SS PHY POR reset */
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+ reset_control_assert(phy->por_rst);
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+
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+ msleep(10);
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+
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+ msleep(10);
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+
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+ /* deassert SS PHY POR reset */
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+ reset_control_deassert(phy->por_rst);
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+
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+ return 0;
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+}
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+
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+static int qca_uni_ss_get_resources(struct platform_device *pdev,
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+ struct qca_uni_ss_phy *phy)
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+{
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+ struct resource *res;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ phy->base = devm_ioremap_resource(phy->dev, res);
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+ if (IS_ERR(phy->base))
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+ return PTR_ERR(phy->base);
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+
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+ phy->por_rst = devm_reset_control_get(phy->dev, "por_rst");
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+ if (IS_ERR(phy->por_rst))
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+ return PTR_ERR(phy->por_rst);
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+
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+ return 0;
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+}
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+
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+static int qca_uni_ss_remove(struct platform_device *pdev)
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+{
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+ struct qca_uni_ss_phy *phy = platform_get_drvdata(pdev);
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+
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+ usb_remove_phy(&phy->phy);
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+ return 0;
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+}
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+
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+static const struct of_device_id qca_uni_ss_id_table[] = {
|
|
+ { .compatible = "qca,uni-ssphy" },
|
|
+ { /* Sentinel */ }
|
|
+};
|
|
+MODULE_DEVICE_TABLE(of, qca_uni_ss_id_table);
|
|
+
|
|
+static int qca_uni_ss_probe(struct platform_device *pdev)
|
|
+{
|
|
+ const struct of_device_id *match;
|
|
+ struct device_node *np = pdev->dev.of_node;
|
|
+ struct qca_uni_ss_phy *phy;
|
|
+ int ret;
|
|
+
|
|
+ match = of_match_device(qca_uni_ss_id_table, &pdev->dev);
|
|
+ if (!match)
|
|
+ return -ENODEV;
|
|
+
|
|
+ phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
|
|
+ if (!phy)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ platform_set_drvdata(pdev, phy);
|
|
+ phy->dev = &pdev->dev;
|
|
+
|
|
+ ret = qca_uni_ss_get_resources(pdev, phy);
|
|
+ if (ret < 0) {
|
|
+ dev_err(&pdev->dev, "failed to request resources: %d\n", ret);
|
|
+ return ret;
|
|
+ }
|
|
+
|
|
+ phy->phy.dev = phy->dev;
|
|
+ phy->phy.label = "qca-uni-ssphy";
|
|
+ phy->phy.init = qca_uni_ss_phy_init;
|
|
+ phy->phy.shutdown = qca_uni_ss_phy_shutdown;
|
|
+ phy->phy.type = USB_PHY_TYPE_USB3;
|
|
+
|
|
+ ret = usb_add_phy_dev(&phy->phy);
|
|
+ return ret;
|
|
+}
|
|
+
|
|
+static struct platform_driver qca_uni_ss_driver = {
|
|
+ .probe = qca_uni_ss_probe,
|
|
+ .remove = qca_uni_ss_remove,
|
|
+ .driver = {
|
|
+ .name = "qca-uni-ssphy",
|
|
+ .owner = THIS_MODULE,
|
|
+ .of_match_table = qca_uni_ss_id_table,
|
|
+ },
|
|
+};
|
|
+
|
|
+module_platform_driver(qca_uni_ss_driver);
|
|
+
|
|
+MODULE_ALIAS("platform:qca-uni-ssphy");
|
|
+MODULE_LICENSE("Dual BSD/GPL");
|
|
+MODULE_DESCRIPTION("USB3 QCA UNI SSPHY driver");
|