80 lines
2.9 KiB
Diff
80 lines
2.9 KiB
Diff
commit 4ede31617056b7424eef28dce59dd6dbe81729c3
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Author: Paul Burton <paul.burton@imgtec.com>
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Date: Tue Sep 22 11:12:17 2015 -0700
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MIPS: CM: make use of mips_cm_{lock,unlock}_other
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Document that CPC core-other accesses must take place within the bounds
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of the CM lock, and begin using the CM lock functions where we access
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the GCRs of other cores. This is required because with CM3 the CPC began
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using GCR_CL_OTHER instead of CPC_CL_OTHER.
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Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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Cc: linux-mips@linux-mips.org
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Cc: Rusty Russell <rusty@rustcorp.com.au>
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Cc: Andrew Bresticker <abrestic@chromium.org>
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Cc: Bjorn Helgaas <bhelgaas@google.com>
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Cc: linux-kernel@vger.kernel.org
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Cc: Niklas Cassel <niklas.cassel@axis.com>
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Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
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Cc: Markos Chandras <markos.chandras@imgtec.com>
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Patchwork: https://patchwork.linux-mips.org/patch/11208/
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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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--- a/arch/mips/include/asm/mips-cpc.h
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+++ b/arch/mips/include/asm/mips-cpc.h
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@@ -149,7 +149,8 @@ BUILD_CPC_Cx_RW(other, 0x10)
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* core: the other core to be accessed
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*
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* Call before operating upon a core via the 'other' register region in
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- * order to prevent the region being moved during access. Must be followed
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+ * order to prevent the region being moved during access. Must be called
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+ * within the bounds of a mips_cm_{lock,unlock}_other pair, and followed
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* by a call to mips_cpc_unlock_other.
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*/
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extern void mips_cpc_lock_other(unsigned int core);
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--- a/arch/mips/kernel/smp-cps.c
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+++ b/arch/mips/kernel/smp-cps.c
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@@ -37,8 +37,9 @@ static unsigned core_vpe_count(unsigned
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if (!config_enabled(CONFIG_MIPS_MT_SMP) || !cpu_has_mipsmt)
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return 1;
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- write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
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+ mips_cm_lock_other(core, 0);
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cfg = read_gcr_co_config() & CM_GCR_Cx_CONFIG_PVPE_MSK;
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+ mips_cm_unlock_other();
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return (cfg >> CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
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}
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@@ -193,7 +194,7 @@ static void boot_core(unsigned core)
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u32 access;
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/* Select the appropriate core */
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- write_gcr_cl_other(core << CM_GCR_Cx_OTHER_CORENUM_SHF);
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+ mips_cm_lock_other(core, 0);
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/* Set its reset vector */
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write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
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@@ -216,6 +217,8 @@ static void boot_core(unsigned core)
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write_gcr_co_reset_release(0);
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}
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+ mips_cm_unlock_other();
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+
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/* The core is now powered up */
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bitmap_set(core_power, core, 1);
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}
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--- a/arch/mips/kernel/smp-gic.c
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+++ b/arch/mips/kernel/smp-gic.c
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@@ -46,9 +46,11 @@ void gic_send_ipi_single(int cpu, unsign
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if (mips_cpc_present() && (core != current_cpu_data.core)) {
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while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
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+ mips_cm_lock_other(core, 0);
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mips_cpc_lock_other(core);
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write_cpc_co_cmd(CPC_Cx_CMD_PWRUP);
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mips_cpc_unlock_other();
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+ mips_cm_unlock_other();
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}
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}
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