576621f1e3
This patch introduces support of new boards with ARC cores.
[1] Synopsys SDP board
This is a new-generation development board from Synopsys that
consists of base-board and CPU tile-board (which might have a real
ASIC or FPGA with CPU image).
It sports a lot of DesignWare peripherals like GMAC, USB, SPI, I2C
etc and is intended to be used for early development of ARC-based
products.
[2] nSIM
This is a virtual board implemented in Synopsys proprietary
software simulator (even though available for free for open source
community). This board has only serial port as a peripheral and so
it is meant to be used for runtime testing which is especially
useful during bring-up of new tools and platforms.
What's also important ARC cores are very configurable so there're
many variations of options like cache sizes, their line lengths,
additional hardware blocks like multipliers, dividers etc. And this
board could be used to make sure built software still runs on
different HW configurations.
Cc: Felix Fietkau <nbd@openwrt.org>
Cc: Jo-Philipp Wich <jow@openwrt.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
SVN-Revision: 47589
224 lines
4.9 KiB
Text
224 lines
4.9 KiB
Text
/*
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* Support for peripherals on the AXS10x mainboard
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*
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* Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/ {
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axs10x_mb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00000000 0xe0000000 0x10000000>;
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interrupt-parent = <&mb_intc>;
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clocks {
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i2cclk: i2cclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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apbclk: apbclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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mmcclk: mmcclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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};
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ethernet@0x18000 {
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#interrupt-cells = <1>;
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compatible = "snps,dwmac";
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reg = < 0x18000 0x2000 >;
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interrupts = < 4 >;
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interrupt-names = "macirq";
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phy-mode = "rgmii";
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snps,pbl = < 32 >;
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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};
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ehci@0x40000 {
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compatible = "generic-ehci";
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reg = < 0x40000 0x100 >;
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interrupts = < 8 >;
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};
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ohci@0x60000 {
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compatible = "generic-ohci";
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reg = < 0x60000 0x100 >;
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interrupts = < 8 >;
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};
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/*
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* According to DW Mobile Storage databook it is required
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* to use "Hold Register" if card is enumerated in SDR12 or
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* SDR25 modes.
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*
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* Utilization of "Hold Register" is already implemented via
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* dw_mci_pltfm_prepare_command() which in its turn gets
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* used through dw_mci_drv_data->prepare_command call-back.
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* This call-back is used in Altera Socfpga platform and so
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* we may reuse it saying that we're compatible with their
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* "altr,socfpga-dw-mshc".
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*
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* Most probably "Hold Register" utilization is platform-
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* independent requirement which means that single unified
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* "snps,dw-mshc" should be enough for all users of DW MMC once
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* dw_mci_pltfm_prepare_command() is used in generic platform
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* code.
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*/
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mmc@0x15000 {
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compatible = "altr,socfpga-dw-mshc";
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reg = < 0x15000 0x400 >;
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num-slots = < 1 >;
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fifo-depth = < 16 >;
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card-detect-delay = < 200 >;
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clocks = <&apbclk>, <&mmcclk>;
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clock-names = "biu", "ciu";
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interrupts = < 7 >;
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bus-width = < 4 >;
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};
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uart@0x20000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x20000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <17>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart@0x21000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x21000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <18>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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/* UART muxed with USB data port (ttyS3) */
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uart@0x22000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x22000 0x100>;
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clock-frequency = <33333333>;
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interrupts = <19>;
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baud = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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i2c@0x1d000 {
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compatible = "snps,designware-i2c";
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reg = <0x1d000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <14>;
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};
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i2c@0x1e000 {
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compatible = "snps,designware-i2c";
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reg = <0x1e000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <15>;
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};
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i2c@0x1f000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1f000 0x100>;
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clock-frequency = <400000>;
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clocks = <&i2cclk>;
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interrupts = <16>;
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eeprom@0x54{
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compatible = "24c01";
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reg = <0x54>;
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pagesize = <0x8>;
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};
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eeprom@0x57{
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compatible = "24c04";
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reg = <0x57>;
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pagesize = <0x8>;
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};
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};
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gpio0:gpio@13000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x13000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio0_banka: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <32>;
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reg = <0>;
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};
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gpio0_bankb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <1>;
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};
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gpio0_bankc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <2>;
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};
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};
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gpio1:gpio@14000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x14000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio1_banka: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <30>;
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reg = <0>;
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};
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gpio1_bankb: gpio-controller@1 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <10>;
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reg = <1>;
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};
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gpio1_bankc: gpio-controller@2 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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snps,nr-gpios = <8>;
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reg = <2>;
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};
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};
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};
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};
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