5b089e45a6
Refresh patches on all 4.4 supported platforms. Compile & run tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
73 lines
2.3 KiB
Diff
73 lines
2.3 KiB
Diff
From 3dbdbeedb865d12700dae53b59e259ea083e6186 Mon Sep 17 00:00:00 2001
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From: Eric Anholt <eric@anholt.net>
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Date: Wed, 1 Jun 2016 12:05:35 -0700
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Subject: [PATCH] clk: bcm2835: Mark the CM SDRAM clock's parent as critical
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While the SDRAM is being driven by its dedicated PLL most of the time,
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there is a little loop running in the firmware that periodically turns
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on the CM SDRAM clock (using its pre-initialized parent) and switches
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SDRAM to using the CM clock to do PVT recalibration.
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This avoids system hangs if we choose SDRAM's parent for some other
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clock, then disable that clock.
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Signed-off-by: Eric Anholt <eric@anholt.net>
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---
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drivers/clk/bcm/clk-bcm2835.c | 25 +++++++++++++++++++++++++
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1 file changed, 25 insertions(+)
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--- a/drivers/clk/bcm/clk-bcm2835.c
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+++ b/drivers/clk/bcm/clk-bcm2835.c
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@@ -36,6 +36,7 @@
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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+#include <linux/clk.h>
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#include <linux/clk/bcm2835.h>
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#include <linux/debugfs.h>
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#include <linux/module.h>
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@@ -1841,6 +1842,25 @@ static const struct bcm2835_clk_desc clk
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.ctl_reg = CM_PERIICTL),
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};
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+/*
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+ * Permanently take a reference on the parent of the SDRAM clock.
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+ *
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+ * While the SDRAM is being driven by its dedicated PLL most of the
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+ * time, there is a little loop running in the firmware that
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+ * periodically switches the SDRAM to using our CM clock to do PVT
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+ * recalibration, with the assumption that the previously configured
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+ * SDRAM parent is still enabled and running.
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+ */
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+static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
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+{
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+ struct clk *parent = clk_get_parent(sdc);
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+
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+ if (IS_ERR(parent))
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+ return PTR_ERR(parent);
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+
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+ return clk_prepare_enable(parent);
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+}
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+
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static int bcm2835_clk_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -1850,6 +1870,7 @@ static int bcm2835_clk_probe(struct plat
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const struct bcm2835_clk_desc *desc;
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const size_t asize = ARRAY_SIZE(clk_desc_array);
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size_t i;
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+ int ret;
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cprman = devm_kzalloc(dev,
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sizeof(*cprman) + asize * sizeof(*clks),
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@@ -1880,6 +1901,10 @@ static int bcm2835_clk_probe(struct plat
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clks[i] = desc->clk_register(cprman, desc->data);
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}
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+ ret = bcm2835_mark_sdc_parent_critical(clks[BCM2835_CLOCK_SDRAM]);
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+ if (ret)
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+ return ret;
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+
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return of_clk_add_provider(dev->of_node, of_clk_src_onecell_get,
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&cprman->onecell);
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}
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