399 lines
10 KiB
Diff
399 lines
10 KiB
Diff
From 9241770134d9bea522051622c52a3195a3d218e0 Mon Sep 17 00:00:00 2001
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From: Lars-Peter Clausen <lars@metafoo.de>
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Date: Sat, 24 Apr 2010 12:12:37 +0200
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Subject: [PATCH] Add jz4740 rtc driver
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---
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drivers/rtc/Kconfig | 11 ++
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drivers/rtc/Makefile | 1 +
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drivers/rtc/rtc-jz4740.c | 344 ++++++++++++++++++++++++++++++++++++++++++++++
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3 files changed, 356 insertions(+), 0 deletions(-)
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create mode 100644 drivers/rtc/rtc-jz4740.c
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diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
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index 6a13037..74699dd 100644
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--- a/drivers/rtc/Kconfig
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+++ b/drivers/rtc/Kconfig
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@@ -488,6 +488,17 @@ config RTC_DRV_EFI
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This driver can also be built as a module. If so, the module
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will be called rtc-efi.
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+config RTC_DRV_JZ4740
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+ tristate "Ingenic JZ4720/JZ4740 SoC"
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+ depends on RTC_CLASS
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+ depends on SOC_JZ4740
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+ help
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+ If you say yes here you get support for the
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+ Ingenic JZ4720/JZ4740 SoC RTC controller.
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+
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+ This driver can also be buillt as a module. If so, the module
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+ will be called rtc-jz4740.
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+
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config RTC_DRV_STK17TA8
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tristate "Simtek STK17TA8"
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depends on RTC_CLASS
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diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
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index 44ef194..7002033 100644
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--- a/drivers/rtc/Makefile
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+++ b/drivers/rtc/Makefile
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@@ -45,6 +45,7 @@ obj-$(CONFIG_RTC_DRV_EP93XX) += rtc-ep93xx.o
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obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o
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obj-$(CONFIG_RTC_DRV_GENERIC) += rtc-generic.o
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obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o
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+obj-$(CONFIG_RTC_DRV_JZ4740) += rtc-jz4740.o
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obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o
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obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o
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obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o
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diff --git a/drivers/rtc/rtc-jz4740.c b/drivers/rtc/rtc-jz4740.c
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new file mode 100644
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index 0000000..aac905a
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--- /dev/null
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+++ b/drivers/rtc/rtc-jz4740.c
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@@ -0,0 +1,344 @@
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+/*
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+ * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
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+ * JZ4720/JZ4740 SoC RTC driver
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/rtc.h>
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+#include <linux/slab.h>
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+#include <linux/spinlock.h>
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+
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+#define JZ_REG_RTC_CTRL 0x00
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+#define JZ_REG_RTC_SEC 0x04
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+#define JZ_REG_RTC_SEC_ALARM 0x08
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+#define JZ_REG_RTC_REGULATOR 0x0C
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+#define JZ_REG_RTC_HIBERNATE 0x20
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+#define JZ_REG_RTC_SCRATCHPAD 0x34
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+
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+#define JZ_RTC_CTRL_WRDY BIT(7)
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+#define JZ_RTC_CTRL_1HZ BIT(6)
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+#define JZ_RTC_CTRL_1HZ_IRQ BIT(5)
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+#define JZ_RTC_CTRL_AF BIT(4)
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+#define JZ_RTC_CTRL_AF_IRQ BIT(3)
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+#define JZ_RTC_CTRL_AE BIT(2)
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+#define JZ_RTC_CTRL_ENABLE BIT(0)
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+
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+struct jz4740_rtc {
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+ struct resource *mem;
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+ void __iomem *base;
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+
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+ struct rtc_device *rtc;
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+
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+ unsigned int irq;
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+
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+ spinlock_t lock;
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+};
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+
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+static inline uint32_t jz4740_rtc_reg_read(struct jz4740_rtc *rtc, size_t reg)
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+{
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+ return readl(rtc->base + reg);
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+}
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+
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+static inline void jz4740_rtc_wait_write_ready(struct jz4740_rtc *rtc)
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+{
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+ uint32_t ctrl;
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+ do {
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+ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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+ } while (!(ctrl & JZ_RTC_CTRL_WRDY));
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+}
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+
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+
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+static inline void jz4740_rtc_reg_write(struct jz4740_rtc *rtc, size_t reg,
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+ uint32_t val)
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+{
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+ jz4740_rtc_wait_write_ready(rtc);
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+ writel(val, rtc->base + reg);
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+}
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+
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+static void jz4740_rtc_ctrl_set_bits(struct jz4740_rtc *rtc, uint32_t mask,
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+ uint32_t val)
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+{
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+ unsigned long flags;
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+ uint32_t ctrl;
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+
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+ spin_lock_irqsave(&rtc->lock, flags);
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+
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+ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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+
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+ /* Don't clear interrupt flags by accident */
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+ ctrl |= JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF;
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+
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+ ctrl &= ~mask;
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+ ctrl |= val;
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+
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+ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_CTRL, ctrl);
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+
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+ spin_unlock_irqrestore(&rtc->lock, flags);
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+}
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+
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+static inline struct jz4740_rtc *dev_to_rtc(struct device *dev)
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+{
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+ return dev_get_drvdata(dev);
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+}
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+
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+static int jz4740_rtc_read_time(struct device *dev, struct rtc_time *time)
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+{
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+ struct jz4740_rtc *rtc = dev_to_rtc(dev);
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+ uint32_t secs, secs2;
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+
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+ secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
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+ secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
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+
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+ while (secs != secs2) {
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+ secs = secs2;
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+ secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC);
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+ }
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+
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+ rtc_time_to_tm(secs, time);
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+
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+ return rtc_valid_tm(time);
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+}
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+
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+static int jz4740_rtc_set_mmss(struct device *dev, unsigned long secs)
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+{
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+ struct jz4740_rtc *rtc = dev_to_rtc(dev);
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+
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+ if ((uint32_t)secs != secs)
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+ return -EINVAL;
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+
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+ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, secs);
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+
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+ return 0;
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+}
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+
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+static int jz4740_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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+{
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+ struct jz4740_rtc *rtc = dev_to_rtc(dev);
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+ uint32_t secs, secs2;
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+ uint32_t ctrl;
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+
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+ secs = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
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+ secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
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+
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+ while (secs != secs2) {
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+ secs = secs2;
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+ secs2 = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SEC_ALARM);
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+ }
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+
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+ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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+
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+ alrm->enabled = !!(ctrl & JZ_RTC_CTRL_AE);
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+ alrm->pending = !!(ctrl & JZ_RTC_CTRL_AF);
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+
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+ rtc_time_to_tm(secs, &alrm->time);
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+
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+ return rtc_valid_tm(&alrm->time);
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+}
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+
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+static int jz4740_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
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+{
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+ struct jz4740_rtc *rtc = dev_to_rtc(dev);
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+ unsigned long secs;
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+
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+ rtc_tm_to_time(&alrm->time, &secs);
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+
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+ if ((uint32_t)secs != secs)
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+ return -EINVAL;
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+
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+ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC_ALARM, (uint32_t)secs);
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+ jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AE,
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+ alrm->enabled ? JZ_RTC_CTRL_AE : 0);
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+
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+ return 0;
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+}
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+
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+static int jz4740_rtc_update_irq_enable(struct device *dev, unsigned int enable)
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+{
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+ struct jz4740_rtc *rtc = dev_to_rtc(dev);
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+ jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ_IRQ,
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+ enable ? JZ_RTC_CTRL_1HZ_IRQ : 0);
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+ return 0;
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+}
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+
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+
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+static int jz4740_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
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+{
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+ struct jz4740_rtc *rtc = dev_to_rtc(dev);
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+ jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_AF_IRQ,
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+ enable ? JZ_RTC_CTRL_AF_IRQ : 0);
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+ return 0;
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+}
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+
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+static struct rtc_class_ops jz4740_rtc_ops = {
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+ .read_time = jz4740_rtc_read_time,
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+ .set_mmss = jz4740_rtc_set_mmss,
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+ .read_alarm = jz4740_rtc_read_alarm,
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+ .set_alarm = jz4740_rtc_set_alarm,
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+ .update_irq_enable = jz4740_rtc_update_irq_enable,
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+ .alarm_irq_enable = jz4740_rtc_alarm_irq_enable,
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+};
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+
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+static irqreturn_t jz4740_rtc_irq(int irq, void *data)
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+{
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+ struct jz4740_rtc *rtc = data;
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+ uint32_t ctrl;
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+ unsigned long events = 0;
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+ ctrl = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_CTRL);
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+
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+ if (ctrl & JZ_RTC_CTRL_1HZ)
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+ events |= (RTC_UF | RTC_IRQF);
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+
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+ if (ctrl & JZ_RTC_CTRL_AF)
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+ events |= (RTC_AF | RTC_IRQF);
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+
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+ rtc_update_irq(rtc->rtc, 1, events);
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+
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+ jz4740_rtc_ctrl_set_bits(rtc, JZ_RTC_CTRL_1HZ | JZ_RTC_CTRL_AF, 0);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+void jz4740_rtc_poweroff(struct device *dev)
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+{
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+ struct jz4740_rtc *rtc = dev_get_drvdata(dev);
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+ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_HIBERNATE, 1);
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+}
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+EXPORT_SYMBOL_GPL(jz4740_rtc_poweroff);
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+
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+static int __devinit jz4740_rtc_probe(struct platform_device *pdev)
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+{
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+ int ret;
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+ struct jz4740_rtc *rtc;
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+ uint32_t scratchpad;
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+
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+ rtc = kmalloc(sizeof(*rtc), GFP_KERNEL);
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+
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+ rtc->irq = platform_get_irq(pdev, 0);
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+
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+ if (rtc->irq < 0) {
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+ ret = -ENOENT;
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+ dev_err(&pdev->dev, "Failed to get platform irq\n");
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+ goto err_free;
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+ }
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+
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+ rtc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!rtc->mem) {
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+ ret = -ENOENT;
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+ dev_err(&pdev->dev, "Failed to get platform mmio memory\n");
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+ goto err_free;
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+ }
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+
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+ rtc->mem = request_mem_region(rtc->mem->start, resource_size(rtc->mem),
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+ pdev->name);
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+
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+ if (!rtc->mem) {
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+ ret = -EBUSY;
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+ dev_err(&pdev->dev, "Failed to request mmio memory region\n");
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+ goto err_free;
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+ }
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+
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+ rtc->base = ioremap_nocache(rtc->mem->start, resource_size(rtc->mem));
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+
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+ if (!rtc->base) {
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+ ret = -EBUSY;
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+ dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
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+ goto err_release_mem_region;
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+ }
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+
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+ spin_lock_init(&rtc->lock);
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+
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+ platform_set_drvdata(pdev, rtc);
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+
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+ rtc->rtc = rtc_device_register(pdev->name, &pdev->dev, &jz4740_rtc_ops,
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+ THIS_MODULE);
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+
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+ if (IS_ERR(rtc->rtc)) {
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+ ret = PTR_ERR(rtc->rtc);
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+ dev_err(&pdev->dev, "Failed to register rtc device: %d\n", ret);
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+ goto err_iounmap;
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+ }
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+
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+ ret = request_irq(rtc->irq, jz4740_rtc_irq, 0,
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+ pdev->name, rtc);
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+
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+ if (ret) {
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+ dev_err(&pdev->dev, "Failed to request rtc irq: %d\n", ret);
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+ goto err_unregister_rtc;
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+ }
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+
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+ scratchpad = jz4740_rtc_reg_read(rtc, JZ_REG_RTC_SCRATCHPAD);
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+ if (scratchpad != 0x12345678) {
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+ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SCRATCHPAD, 0x12345678);
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+ jz4740_rtc_reg_write(rtc, JZ_REG_RTC_SEC, 0);
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+ }
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+
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+ return 0;
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+
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+err_unregister_rtc:
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+ rtc_device_unregister(rtc->rtc);
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+err_iounmap:
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+ platform_set_drvdata(pdev, NULL);
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+ iounmap(rtc->base);
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+err_release_mem_region:
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+ release_mem_region(rtc->mem->start, resource_size(rtc->mem));
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+err_free:
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+ kfree(rtc);
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+
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+ return ret;
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+}
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+
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+static int __devexit jz4740_rtc_remove(struct platform_device *pdev)
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+{
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+ struct jz4740_rtc *rtc = platform_get_drvdata(pdev);
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+
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+ free_irq(rtc->irq, rtc);
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+
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+ rtc_device_unregister(rtc->rtc);
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+
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+ iounmap(rtc->base);
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+ release_mem_region(rtc->mem->start, resource_size(rtc->mem));
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+
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+ kfree(rtc);
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+
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+ platform_set_drvdata(pdev, NULL);
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+
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+ return 0;
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+}
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+
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+struct platform_driver jz4740_rtc_driver = {
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+ .probe = jz4740_rtc_probe,
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+ .remove = __devexit_p(jz4740_rtc_remove),
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+ .driver = {
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+ .name = "jz4740-rtc",
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+ .owner = THIS_MODULE,
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+ },
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+};
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+
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+static int __init jz4740_rtc_init(void)
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+{
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+ return platform_driver_register(&jz4740_rtc_driver);
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+}
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+module_init(jz4740_rtc_init);
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+
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+static void __exit jz4740_rtc_exit(void)
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+{
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+ platform_driver_unregister(&jz4740_rtc_driver);
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+}
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+module_exit(jz4740_rtc_exit);
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+
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+MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
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+MODULE_LICENSE("GPL");
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+MODULE_DESCRIPTION("RTC driver for the JZ4720/JZ4740 SoC\n");
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+MODULE_ALIAS("platform:jz4740-rtc");
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--
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1.5.6.5
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