341 lines
9.6 KiB
Diff
341 lines
9.6 KiB
Diff
From 1db0d19afe5830f7d020c7c5386be8cc20cf0f15 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 23 May 2013 18:45:29 +0200
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Subject: [PATCH 61/79] DMA: MIPS: ralink: add dmaengine driver
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/dma/Kconfig | 7 ++
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drivers/dma/Makefile | 1 +
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drivers/dma/ralink_gdma.c | 229 +++++++++++++++++++++++++++++++++++++++++++++
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drivers/dma/ralink_gdma.h | 55 +++++++++++
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4 files changed, 292 insertions(+)
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create mode 100644 drivers/dma/ralink_gdma.c
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create mode 100644 drivers/dma/ralink_gdma.h
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diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
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index d4c1218..323f684 100644
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--- a/drivers/dma/Kconfig
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+++ b/drivers/dma/Kconfig
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@@ -320,6 +320,13 @@ config MMP_PDMA
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help
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Support the MMP PDMA engine for PXA and MMP platfrom.
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+config RALINK_GDMA
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+ bool "Ralink Generic DMA support"
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+ depends on RALINK
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+ select DMA_ENGINE
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+ help
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+ Support the GDMA engine for MIPS based Ralink SoC.
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+
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config DMA_ENGINE
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bool
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diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
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index 7428fea..a981e2c 100644
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--- a/drivers/dma/Makefile
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+++ b/drivers/dma/Makefile
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@@ -34,3 +34,4 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
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obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
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obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
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+obj-$(CONFIG_RALINK_GDMA) += ralink_gdma.o
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diff --git a/drivers/dma/ralink_gdma.c b/drivers/dma/ralink_gdma.c
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new file mode 100644
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index 0000000..be7c317
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--- /dev/null
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+++ b/drivers/dma/ralink_gdma.c
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@@ -0,0 +1,229 @@
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+#include <linux/init.h>
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+#include <linux/module.h>
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+#include <linux/slab.h>
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+#include <linux/delay.h>
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+#include <linux/dma-mapping.h>
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+#include <linux/spinlock.h>
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+#include <linux/interrupt.h>
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+#include <linux/platform_device.h>
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+#include <linux/of_platform.h>
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+#include <linux/memory.h>
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+
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+#include "ralink_gdma.h"
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+
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+#define SURFBOARDINT_DMA 10
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+#define MEMCPY_DMA_CH 8
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+#define to_rt2880_dma_chan(chan) \
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+ container_of(chan, struct rt2880_dma_chan, common)
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+
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+static dma_cookie_t rt2880_dma_tx_submit(struct dma_async_tx_descriptor *tx)
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+{
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+ dma_cookie_t cookie;
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+
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+ cookie = tx->chan->cookie;
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+
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+ return cookie;
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+}
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+
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+#define MIN_RTDMA_PKT_LEN 128
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+static struct dma_async_tx_descriptor *
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+rt2880_dma_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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+ size_t len, unsigned long flags)
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+{
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+ struct rt2880_dma_chan *rt_chan = to_rt2880_dma_chan(chan);
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+ unsigned long mid_offset;
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+
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+ spin_lock_bh(&rt_chan->lock);
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+
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+ if(len < MIN_RTDMA_PKT_LEN) {
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+ memcpy(phys_to_virt(dest), phys_to_virt(src), len);
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+ } else {
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+ mid_offset = len/2;
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+
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+ /* Lower parts are transferred by GDMA.
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+ * Upper parts are transferred by CPU.
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+ */
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+ RT_DMA_WRITE_REG(RT_DMA_SRC_REG(MEMCPY_DMA_CH), src);
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+ RT_DMA_WRITE_REG(RT_DMA_DST_REG(MEMCPY_DMA_CH), dest);
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+ RT_DMA_WRITE_REG(RT_DMA_CTRL_REG(MEMCPY_DMA_CH), (mid_offset << 16) | (3 << 3) | (3 << 0));
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+
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+ memcpy(phys_to_virt(dest)+mid_offset, phys_to_virt(src)+mid_offset, len-mid_offset);
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+
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+ dma_async_tx_descriptor_init(&rt_chan->txd, chan);
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+
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+ while((RT_DMA_READ_REG(RT_DMA_DONEINT) & (0x1<<MEMCPY_DMA_CH))==0);
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+ RT_DMA_WRITE_REG(RT_DMA_DONEINT, (1<<MEMCPY_DMA_CH));
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+ }
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+
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+ spin_unlock_bh(&rt_chan->lock);
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+
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+ return &rt_chan->txd;
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+}
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+
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+/**
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+ * rt2880_dma_status - poll the status of an XOR transaction
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+ * @chan: XOR channel handle
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+ * @cookie: XOR transaction identifier
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+ * @txstate: XOR transactions state holder (or NULL)
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+ */
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+static enum dma_status rt2880_dma_status(struct dma_chan *chan,
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+ dma_cookie_t cookie,
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+ struct dma_tx_state *txstate)
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+{
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+ return 0;
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+}
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+
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+static irqreturn_t rt2880_dma_interrupt_handler(int irq, void *data)
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+{
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+
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+ printk("%s\n",__FUNCTION__);
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+
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+ return IRQ_HANDLED;
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+}
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+
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+static void rt2880_dma_issue_pending(struct dma_chan *chan)
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+{
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+}
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+
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+static int rt2880_dma_alloc_chan_resources(struct dma_chan *chan)
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+{
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+// printk("%s\n",__FUNCTION__);
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+
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+ return 0;
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+}
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+
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+static void rt2880_dma_free_chan_resources(struct dma_chan *chan)
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+{
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+// printk("%s\n",__FUNCTION__);
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+
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+}
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+
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+static int rt2880_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, unsigned long arg)
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+{
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+ switch (cmd) {
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+ case DMA_TERMINATE_ALL:
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+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
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+ break;
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+ case DMA_SLAVE_CONFIG:
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+ printk("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
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+ break;
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+ default:
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+ return -ENXIO;
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+ }
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+
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+ return 0;
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+}
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+
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+static int rt2880_dma_probe(struct platform_device *pdev)
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+{
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+ struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ __iomem void *membase;
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+ struct dma_device *dma_dev;
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+ struct rt2880_dma_chan *rt_chan;
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+ int err;
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+ int ret;
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+ int reg;
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+ int irq;
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+
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+ membase = devm_request_and_ioremap(&pdev->dev, res);
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+ if (IS_ERR(membase))
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+ return PTR_ERR(membase);
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+
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+ dma_dev = devm_kzalloc(&pdev->dev, sizeof(*dma_dev), GFP_KERNEL);
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+ if (!dma_dev)
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+ return -ENOMEM;
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+
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+ irq = platform_get_irq(pdev, 0);
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+ if (!irq) {
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+ dev_err(&pdev->dev, "failed to load irq\n");
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+ return -ENOENT;
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+ }
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+
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+
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+ INIT_LIST_HEAD(&dma_dev->channels);
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+ dma_cap_zero(dma_dev->cap_mask);
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+ dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
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+ dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
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+ dma_dev->device_alloc_chan_resources = rt2880_dma_alloc_chan_resources;
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+ dma_dev->device_free_chan_resources = rt2880_dma_free_chan_resources;
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+ dma_dev->device_tx_status = rt2880_dma_status;
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+ dma_dev->device_issue_pending = rt2880_dma_issue_pending;
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+ dma_dev->device_prep_dma_memcpy = rt2880_dma_prep_dma_memcpy;
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+ dma_dev->device_control = rt2880_dma_control;
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+ dma_dev->dev = &pdev->dev;
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+
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+ rt_chan = devm_kzalloc(&pdev->dev, sizeof(*rt_chan), GFP_KERNEL);
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+ if (!rt_chan) {
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+ return -ENOMEM;
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+ }
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+
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+ spin_lock_init(&rt_chan->lock);
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+ INIT_LIST_HEAD(&rt_chan->chain);
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+ INIT_LIST_HEAD(&rt_chan->completed_slots);
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+ INIT_LIST_HEAD(&rt_chan->all_slots);
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+ rt_chan->common.device = dma_dev;
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+ rt_chan->txd.tx_submit = rt2880_dma_tx_submit;
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+
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+ list_add_tail(&rt_chan->common.device_node, &dma_dev->channels);
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+
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+ err = dma_async_device_register(dma_dev);
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+ if (0 != err) {
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+ pr_err("ERR_MDMA:device_register failed: %d\n", err);
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+ return 1;
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+ }
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+
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+ ret = request_irq(irq, rt2880_dma_interrupt_handler, 0, dev_name(&pdev->dev), NULL);
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+ if(ret){
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+ pr_err("IRQ %d is not free.\n", SURFBOARDINT_DMA);
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+ return 1;
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+ }
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+
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+ //set GDMA register in advance.
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+ reg = (32 << 16) | (32 << 8) | (MEMCPY_DMA_CH << 3);
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+ RT_DMA_WRITE_REG(RT_DMA_CTRL_REG1(MEMCPY_DMA_CH), reg);
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+
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+ dev_info(&pdev->dev, "running\n");
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+
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+ return 0;
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+}
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+
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+static int rt2880_dma_remove(struct platform_device *dev)
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+{
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+ struct dma_device *dma_dev = platform_get_drvdata(dev);
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+
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+ printk("%s\n",__FUNCTION__);
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+
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+ dma_async_device_unregister(dma_dev);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id rt2880_dma_match[] = {
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+ { .compatible = "ralink,rt2880-gdma" },
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+ {},
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+};
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+MODULE_DEVICE_TABLE(of, rt2880_wdt_match);
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+
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+static struct platform_driver rt2880_dma_driver = {
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+ .probe = rt2880_dma_probe,
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+ .remove = rt2880_dma_remove,
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+ .driver = {
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+ .owner = THIS_MODULE,
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+ .name = RT_DMA_NAME,
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+ .of_match_table = rt2880_dma_match,
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+ },
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+};
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+
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+static int __init rt2880_dma_init(void)
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+{
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+ int rc;
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+
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+ rc = platform_driver_register(&rt2880_dma_driver);
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+ return rc;
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+}
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+module_init(rt2880_dma_init);
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+
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+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
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+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
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+MODULE_DESCRIPTION("DMA engine driver for Ralink DMA engine");
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+MODULE_LICENSE("GPL");
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diff --git a/drivers/dma/ralink_gdma.h b/drivers/dma/ralink_gdma.h
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new file mode 100644
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index 0000000..73e1948
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--- /dev/null
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+++ b/drivers/dma/ralink_gdma.h
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@@ -0,0 +1,55 @@
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+/*
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+ * Copyright (C) 2007, 2008, Marvell International Ltd.
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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+ * for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software Foundation,
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+ * Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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+ */
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+
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+#ifndef RT_DMA_H
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+#define RT_DMA_H
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+
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+#include <linux/types.h>
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+#include <linux/io.h>
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+#include <linux/dmaengine.h>
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+#include <linux/interrupt.h>
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+
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+#define RT_DMA_NAME "rt2880_dma"
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+
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+#define RALINK_GDMA_BASE 0xB0002800
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+
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+struct rt2880_dma_chan {
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+ int pending;
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+ dma_cookie_t completed_cookie;
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+ spinlock_t lock; /* protects the descriptor slot pool */
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+ void __iomem *mmr_base;
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+ unsigned int idx;
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+ enum dma_transaction_type current_type;
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+ struct dma_async_tx_descriptor txd;
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+ struct list_head chain;
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+ struct list_head completed_slots;
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+ struct dma_chan common;
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+ struct list_head all_slots;
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+ int slots_allocated;
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+ struct tasklet_struct irq_tasklet;
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+};
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+
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+#define RT_DMA_READ_REG(addr) le32_to_cpu(*(volatile u32 *)(addr))
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+#define RT_DMA_WRITE_REG(addr, val) *((volatile uint32_t *)(addr)) = cpu_to_le32(val)
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+
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+#define RT_DMA_SRC_REG(ch) (RALINK_GDMA_BASE + ch*16)
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+#define RT_DMA_DST_REG(ch) (RT_DMA_SRC_REG(ch) + 4)
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+#define RT_DMA_CTRL_REG(ch) (RT_DMA_DST_REG(ch) + 4)
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+#define RT_DMA_CTRL_REG1(ch) (RT_DMA_CTRL_REG(ch) + 4)
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+#define RT_DMA_DONEINT (RALINK_GDMA_BASE + 0x204)
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+
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+#endif
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--
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1.7.10.4
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