315 lines
6.7 KiB
C
315 lines
6.7 KiB
C
/*
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* arch/arm/mach-ox820/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/jiffies.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/dma-mapping.h>
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#include <linux/cache.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_scu.h>
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#include <asm/tlbflush.h>
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#include <asm/cputype.h>
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#include <linux/delay.h>
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#include <asm/fiq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/iomap.h>
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#include <mach/smp.h>
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#include <mach/hardware.h>
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#include <mach/irqs.h>
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#ifdef CONFIG_DMA_CACHE_FIQ_BROADCAST
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#define FIQ_GENERATE 0x00000002
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#define OXNAS_MAP_AREA 0x01000000
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#define OXNAS_UNMAP_AREA 0x02000000
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#define OXNAS_FLUSH_RANGE 0x03000000
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struct fiq_req {
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union {
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struct {
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const void *addr;
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size_t size;
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} map;
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struct {
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const void *addr;
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size_t size;
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} unmap;
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struct {
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const void *start;
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const void *end;
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} flush;
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};
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volatile uint flags;
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void __iomem *reg;
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} ____cacheline_aligned;
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static struct fiq_handler fh = {
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.name = "oxnas-fiq"
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};
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DEFINE_PER_CPU(struct fiq_req, fiq_data);
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static inline void ox820_set_fiq_regs(unsigned int cpu)
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{
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struct pt_regs FIQ_regs;
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struct fiq_req *fiq_req = &per_cpu(fiq_data, !cpu);
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FIQ_regs.ARM_r8 = 0;
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FIQ_regs.ARM_ip = (unsigned int)fiq_req;
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FIQ_regs.ARM_sp = (int)(cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT);
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fiq_req->reg = cpu ? RPSC_IRQ_SOFT : RPSA_IRQ_SOFT;
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set_fiq_regs(&FIQ_regs);
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}
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static void __init ox820_init_fiq(void)
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{
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void *fiqhandler_start;
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unsigned int fiqhandler_length;
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int ret;
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fiqhandler_start = &ox820_fiq_start;
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fiqhandler_length = &ox820_fiq_end - &ox820_fiq_start;
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ret = claim_fiq(&fh);
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if (ret)
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return;
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set_fiq_handler(fiqhandler_start, fiqhandler_length);
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writel(IRQ_SOFT, RPSA_FIQ_IRQ_TO_FIQ);
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writel(1, RPSA_FIQ_ENABLE);
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writel(IRQ_SOFT, RPSC_FIQ_IRQ_TO_FIQ);
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writel(1, RPSC_FIQ_ENABLE);
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}
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void fiq_dma_map_area(const void *addr, size_t size, int dir)
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{
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unsigned long flags;
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struct fiq_req *req;
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raw_local_irq_save(flags);
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/* currently, not possible to take cpu0 down, so only check cpu1 */
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if (!cpu_online(1)) {
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raw_local_irq_restore(flags);
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v6_dma_map_area(addr, size, dir);
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return;
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}
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req = this_cpu_ptr(&fiq_data);
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req->map.addr = addr;
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req->map.size = size;
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req->flags = dir | OXNAS_MAP_AREA;
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smp_mb();
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writel_relaxed(FIQ_GENERATE, req->reg);
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v6_dma_map_area(addr, size, dir);
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while (req->flags)
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barrier();
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raw_local_irq_restore(flags);
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}
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void fiq_dma_unmap_area(const void *addr, size_t size, int dir)
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{
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unsigned long flags;
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struct fiq_req *req;
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raw_local_irq_save(flags);
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/* currently, not possible to take cpu0 down, so only check cpu1 */
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if (!cpu_online(1)) {
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raw_local_irq_restore(flags);
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v6_dma_unmap_area(addr, size, dir);
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return;
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}
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req = this_cpu_ptr(&fiq_data);
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req->unmap.addr = addr;
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req->unmap.size = size;
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req->flags = dir | OXNAS_UNMAP_AREA;
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smp_mb();
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writel_relaxed(FIQ_GENERATE, req->reg);
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v6_dma_unmap_area(addr, size, dir);
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while (req->flags)
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barrier();
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raw_local_irq_restore(flags);
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}
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void fiq_dma_flush_range(const void *start, const void *end)
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{
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unsigned long flags;
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struct fiq_req *req;
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raw_local_irq_save(flags);
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/* currently, not possible to take cpu0 down, so only check cpu1 */
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if (!cpu_online(1)) {
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raw_local_irq_restore(flags);
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v6_dma_flush_range(start, end);
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return;
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}
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req = this_cpu_ptr(&fiq_data);
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req->flush.start = start;
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req->flush.end = end;
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req->flags = OXNAS_FLUSH_RANGE;
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smp_mb();
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writel_relaxed(FIQ_GENERATE, req->reg);
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v6_dma_flush_range(start, end);
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while (req->flags)
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barrier();
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raw_local_irq_restore(flags);
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}
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void fiq_flush_kern_dcache_area(void *addr, size_t size)
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{
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fiq_dma_flush_range(addr, addr + size);
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}
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#else
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#define ox820_set_fiq_regs(cpu) do {} while (0) /* nothing */
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#define ox820_init_fiq() do {} while (0) /* nothing */
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#endif /* DMA_CACHE_FIQ_BROADCAST */
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static DEFINE_SPINLOCK(boot_lock);
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void ox820_secondary_init(unsigned int cpu)
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{
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/*
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* Setup Secondary Core FIQ regs
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*/
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ox820_set_fiq_regs(1);
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/*
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* let the primary processor know we're out of the
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* pen, then head off into the C entry point
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*/
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write_pen_release(-1);
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/*
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* Synchronise with the boot thread.
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*/
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spin_lock(&boot_lock);
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spin_unlock(&boot_lock);
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}
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int ox820_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long timeout;
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/*
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* Set synchronisation state between this boot processor
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* and the secondary one
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*/
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spin_lock(&boot_lock);
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/*
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* This is really belt and braces; we hold unintended secondary
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* CPUs in the holding pen until we're ready for them. However,
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* since we haven't sent them a soft interrupt, they shouldn't
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* be there.
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*/
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write_pen_release(cpu);
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writel(1, IOMEM(OXNAS_GICN_BASE_VA(cpu) + GIC_CPU_CTRL));
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/*
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* Send the secondary CPU a soft interrupt, thereby causing
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* the boot monitor to read the system wide flags register,
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* and branch to the address found there.
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*/
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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timeout = jiffies + (1 * HZ);
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while (time_before(jiffies, timeout)) {
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smp_rmb();
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if (read_pen_release() == -1)
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break;
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udelay(10);
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}
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/*
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* now the secondary core is starting up let it run its
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* calibrations, then wait for it to finish
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*/
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spin_unlock(&boot_lock);
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return read_pen_release() != -1 ? -ENOSYS : 0;
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}
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void *scu_base_addr(void)
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{
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return IOMEM(OXNAS_SCU_BASE_VA);
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init ox820_smp_init_cpus(void)
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{
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void __iomem *scu_base = scu_base_addr();
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unsigned int i, ncores;
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ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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/* sanity check */
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if (ncores > nr_cpu_ids) {
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pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
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ncores, nr_cpu_ids);
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ncores = nr_cpu_ids;
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}
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for (i = 0; i < ncores; i++)
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set_cpu_possible(i, true);
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}
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static void __init ox820_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base_addr());
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/*
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* Write the address of secondary startup into the
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* system-wide flags register. The BootMonitor waits
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* until it receives a soft interrupt, and then the
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* secondary CPU branches to this address.
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*/
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writel(virt_to_phys(ox820_secondary_startup),
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HOLDINGPEN_LOCATION);
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ox820_init_fiq();
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ox820_set_fiq_regs(0);
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}
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struct smp_operations ox820_smp_ops __initdata = {
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.smp_init_cpus = ox820_smp_init_cpus,
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.smp_prepare_cpus = ox820_smp_prepare_cpus,
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.smp_secondary_init = ox820_secondary_init,
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.smp_boot_secondary = ox820_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = ox820_cpu_die,
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#endif
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};
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