02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
127 lines
3.4 KiB
Diff
127 lines
3.4 KiB
Diff
From c57b781689bba48dad635caf005962cc9c8e5e3d Mon Sep 17 00:00:00 2001
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From: Chen-Yu Tsai <wens@csie.org>
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Date: Mon, 3 Feb 2014 09:51:44 +0800
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Subject: [PATCH] ARM: dts: sun7i: rename clock node names to clk@N
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Device tree naming conventions state that node names should match
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node function. Change fully functioning clock nodes to match and
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add clock-output-names to all sunxi clock nodes.
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Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun7i-a20.dtsi | 25 +++++++++++++++++--------
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1 file changed, 17 insertions(+), 8 deletions(-)
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -62,11 +62,12 @@
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#size-cells = <1>;
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ranges;
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- osc24M: osc24M@01c20050 {
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+ osc24M: clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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clock-frequency = <24000000>;
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+ clock-output-names = "osc24M";
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};
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osc32k: clk@0 {
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@@ -76,21 +77,23 @@
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clock-output-names = "osc32k";
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};
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- pll1: pll1@01c20000 {
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+ pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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+ clock-output-names = "pll1";
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};
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- pll4: pll4@01c20018 {
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+ pll4: clk@01c20018 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20018 0x4>;
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clocks = <&osc24M>;
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+ clock-output-names = "pll4";
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};
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- pll5: pll5@01c20020 {
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+ pll5: clk@01c20020 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll5-clk";
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reg = <0x01c20020 0x4>;
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@@ -98,7 +101,7 @@
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clock-output-names = "pll5_ddr", "pll5_other";
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};
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- pll6: pll6@01c20028 {
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+ pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-pll6-clk";
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reg = <0x01c20028 0x4>;
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@@ -111,6 +114,7 @@
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
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+ clock-output-names = "cpu";
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};
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axi: axi@01c20054 {
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@@ -118,6 +122,7 @@
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compatible = "allwinner,sun4i-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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+ clock-output-names = "axi";
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};
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ahb: ahb@01c20054 {
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@@ -125,9 +130,10 @@
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compatible = "allwinner,sun4i-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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+ clock-output-names = "ahb";
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};
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- ahb_gates: ahb_gates@01c20060 {
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+ ahb_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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@@ -152,9 +158,10 @@
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compatible = "allwinner,sun4i-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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+ clock-output-names = "apb0";
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};
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- apb0_gates: apb0_gates@01c20068 {
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+ apb0_gates: clk@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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@@ -170,6 +177,7 @@
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
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+ clock-output-names = "apb1_mux";
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};
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apb1: apb1@01c20058 {
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@@ -177,9 +185,10 @@
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compatible = "allwinner,sun4i-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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+ clock-output-names = "apb1";
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};
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- apb1_gates: apb1_gates@01c2006c {
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+ apb1_gates: clk@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun7i-a20-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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