176 lines
5.4 KiB
Diff
176 lines
5.4 KiB
Diff
From 97478bae3a11b5e87d61b88267e915f7c5ddf4e9 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Wed, 6 Jan 2016 21:55:10 +0100
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Subject: [PATCH 24/81] dt-bindings: add MediaTek PCIe binding documentation
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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.../devicetree/bindings/pci/mediatek-pcie.txt | 140 ++++++++++++++++++++
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arch/arm/boot/dts/mt7623.dtsi | 12 ++
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2 files changed, 152 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
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@@ -0,0 +1,140 @@
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+Mediatek PCIe controller
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+
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+Required properties:
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+- compatible: Should be one of:
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+ - "mediatek,mt2701-pcie"
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+ - "mediatek,mt7623-pcie"
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+- device_type: Must be "pci"
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+- reg: A list of physical base address and length for each set of controller
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+ registers. A list of register ranges to use. Must contain an
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+ entry for each entry in the reg-names property.
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+- reg-names: Must include the following entries:
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+ "pcie": PCIe registers
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+ "pcie phy0": PCIe PHY0 registers
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+ "pcie phy1": PCIe PHY0 registers
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+ "pcie phy2": PCIe PHY0 registers
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+- interrupts: A list of interrupt outputs of the controller. Must contain an
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+ entry for each entry in the interrupt-names property.
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+- interrupt-names: Must include the following entries:
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+ "pcie0": The interrupt that is asserted for port0
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+ "pcie1": The interrupt that is asserted for port1
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+ "pcie2": The interrupt that is asserted for port2
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+- bus-range: Range of bus numbers associated with this controller
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+- #address-cells: Address representation for root ports (must be 3)
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+- #size-cells: Size representation for root ports (must be 2)
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+- ranges: Describes the translation of addresses for root ports and standard
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+ PCI regions. The entries must be 6 cells each.
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+ Please refer to the standard PCI bus binding document for a more detailed
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+ explanation.
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+- #interrupt-cells: Size representation for interrupts (must be 1)
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+- clocks: Must contain an entry for each entry in clock-names.
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+ See ../clocks/clock-bindings.txt for details.
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+- clock-names: Must include the following entries:
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+ - pcie0
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+ - pcie1
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+ - pcie2
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+- resets: Must contain an entry for each entry in reset-names.
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+ See ../reset/reset.txt for details.
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+- reset-names: Must include the following entries:
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+ - pcie0
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+ - pcie1
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+ - pcie2
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+- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range.
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+Root ports are defined as subnodes of the PCIe controller node.
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+
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+Required properties:
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+- device_type: Must be "pci"
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+- assigned-addresses: Address and size of the port configuration registers
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+- reg: PCI bus address of the root port
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+- #address-cells: Must be 3
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+- #size-cells: Must be 2
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+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
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+ property is sufficient.
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+
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+Example:
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+
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+SoC DTSI:
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+
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+ hifsys: clock-controller@1a000000 {
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+ compatible = "mediatek,mt7623-hifsys",
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+ "mediatek,mt2701-hifsys",
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+ "syscon";
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+ reg = <0 0x1a000000 0 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ pcie-controller@1a140000 {
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+ compatible = "mediatek,mt7623-pcie";
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+ device_type = "pci";
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+ reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
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+ <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
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+ <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
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+ <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
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+ reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
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+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie0", "pcie1", "pcie2";
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+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
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+ clock-names = "pcie";
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+ power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
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+ resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
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+ <&hifsys MT2701_HIFSYS_PCIE1_RST>,
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+ <&hifsys MT2701_HIFSYS_PCIE2_RST>;
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+ reset-names = "pcie0", "pice1", "pcie2";
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+
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+ bus-range = <0x00 0xff>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+
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+ mediatek,hifsys = <&hifsys>;
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+
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+ ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
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+ 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
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+
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+ status = "disabled";
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+
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+ pcie@1,0 {
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+ device_type = "pci";
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+ reg = <0x0800 0 0 0 0>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie@2,0{
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+ device_type = "pci";
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+ reg = <0x1000 0 0 0 0>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie@3,0{
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+ device_type = "pci";
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+ reg = <0x1800 0 0 0 0>;
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+
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ ranges;
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+
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+ status = "disabled";
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+ };
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+ };
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+
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+Board DTS:
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+
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+ pcie-controller {
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+ status = "okay";
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+
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+ pci@1,0 {
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+ status = "okay";
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+ };
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+ };
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--- a/arch/arm/boot/dts/mt7623.dtsi
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+++ b/arch/arm/boot/dts/mt7623.dtsi
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@@ -292,6 +292,18 @@
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status = "disabled";
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};
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+ nand: nfi@1100d000 {
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+ compatible = "mediatek,mt2701-nfc";
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+ reg = <0 0x1100d000 0 0x1000>, <0 0x1100e000 0 0x1000>;
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+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>,
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+ <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&pericfg CLK_PERI_NFI>, <&pericfg CLK_PERI_NFI_ECC>,
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+ <&pericfg CLK_PERI_NFI_PAD>;
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+ clock-names = "nfi_clk", "nfiecc_clk", "pad_clk";
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+ nand-on-flash-bbt;
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+ status = "disabled";
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+ };
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+
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7623-mmc",
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"mediatek,mt8135-mmc";
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