90 lines
3.1 KiB
Diff
90 lines
3.1 KiB
Diff
From 4ede4fbb485d0a88839df1f02371fc00755db636 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 7 Dec 2015 17:31:41 +0100
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Subject: [PATCH 23/53] arch: mips: ralink: unify soc id
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/ralink/mt7620.c | 19 ++++++++-----------
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1 file changed, 8 insertions(+), 11 deletions(-)
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diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
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index da734e2..db99e9c 100644
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--- a/arch/mips/ralink/mt7620.c
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+++ b/arch/mips/ralink/mt7620.c
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@@ -37,9 +37,6 @@
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#define PMU1_CFG 0x8C
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#define DIG_SW_SEL BIT(25)
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-/* is this a MT7620 or a MT7628 */
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-enum mt762x_soc_type mt762x_soc;
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-
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/* clock scaling */
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#define CLKCFG_FDIV_MASK 0x1f00
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#define CLKCFG_FDIV_USB_VAL 0x0300
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@@ -410,7 +407,7 @@ void __init ralink_clk_init(void)
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#define RINT(x) ((x) / 1000000)
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#define RFRAC(x) (((x) / 1000) % 1000)
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- if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688) {
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+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
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if (xtal_rate == MHZ(40))
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cpu_rate = MHZ(580);
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else
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@@ -455,7 +452,7 @@ void __init ralink_clk_init(void)
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ralink_clk_add("10180000.wmac", xtal_rate);
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if (IS_ENABLED(CONFIG_USB) &&
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- (mt762x_soc == MT762X_SOC_MT7620A || mt762x_soc == MT762X_SOC_MT7620N)) {
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+ (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7620N)) {
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/*
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* When the CPU goes into sleep mode, the BUS clock will be too low for
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* USB to function properly
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@@ -543,11 +540,11 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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if (n0 == MT7620_CHIP_NAME0 && n1 == MT7620_CHIP_NAME1) {
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if (bga) {
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- mt762x_soc = MT762X_SOC_MT7620A;
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+ ralink_soc = MT762X_SOC_MT7620A;
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name = "MT7620A";
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soc_info->compatible = "ralink,mt7620a-soc";
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} else {
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- mt762x_soc = MT762X_SOC_MT7620N;
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+ ralink_soc = MT762X_SOC_MT7620N;
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name = "MT7620N";
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soc_info->compatible = "ralink,mt7620n-soc";
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}
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@@ -555,10 +552,10 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
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if (efuse & EFUSE_MT7688) {
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- mt762x_soc = MT762X_SOC_MT7688;
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+ ralink_soc = MT762X_SOC_MT7688;
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name = "MT7688";
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} else {
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- mt762x_soc = MT762X_SOC_MT7628AN;
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+ ralink_soc = MT762X_SOC_MT7628AN;
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name = "MT7628AN";
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}
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soc_info->compatible = "ralink,mt7628an-soc";
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@@ -580,7 +577,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
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soc_info->mem_base = MT7620_DRAM_BASE;
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- if (mt762x_soc == MT762X_SOC_MT7628AN)
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+ if (ralink_soc == MT762X_SOC_MT7628AN)
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mt7628_dram_init(soc_info);
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else
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mt7620_dram_init(soc_info);
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@@ -593,7 +590,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
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pr_info("Digital PMU set to %s control\n",
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(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
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- if (mt762x_soc == MT762X_SOC_MT7628AN || mt762x_soc == MT762X_SOC_MT7688)
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+ if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688)
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rt2880_pinmux_data = mt7628an_pinmux_data;
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else
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rt2880_pinmux_data = mt7620a_pinmux_data;
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--
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1.7.10.4
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