bc4f2c5ce4
According to the AR7242 datasheet section 2.8, AR724X CPUs use a 40MHz input clock as the REF_CLK instead of 5MHz. The correct CPU PLL calculation procedure is as follows: CPU_PLL = (DIV * REF_CLK) / REF_DIV / 2. This patch is compatible with the current calculation procedure with default DIV and REF_DIV values. Test on both AR7240, AR7241 and AR7242. Signed-off-by: Weijie Gao <hackpascal@gmail.com> SVN-Revision: 46856
22 lines
562 B
Diff
22 lines
562 B
Diff
--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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@@ -25,7 +25,7 @@
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#include "common.h"
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#define AR71XX_BASE_FREQ 40000000
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-#define AR724X_BASE_FREQ 5000000
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+#define AR724X_BASE_FREQ 40000000
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#define AR913X_BASE_FREQ 5000000
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struct clk {
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@@ -99,8 +99,8 @@
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div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
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freq = div * ref_rate;
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- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
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- freq *= div;
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+ div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
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+ freq /= div;
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cpu_rate = freq;
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