473 lines
11 KiB
Diff
473 lines
11 KiB
Diff
From d5c54ff3d1db0a4348fa04d8e78f3bf6063e3afc Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Mon, 7 Dec 2015 17:21:27 +0100
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Subject: [PATCH 45/53] i2c: add mt7621 driver
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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drivers/i2c/busses/Kconfig | 4 +
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drivers/i2c/busses/Makefile | 1 +
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drivers/i2c/busses/i2c-mt7621.c | 303 +++++++++++++++++++++++++++++++++++++++
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3 files changed, 308 insertions(+)
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create mode 100644 drivers/i2c/busses/i2c-mt7621.c
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--- a/drivers/i2c/busses/Kconfig
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+++ b/drivers/i2c/busses/Kconfig
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@@ -815,6 +815,11 @@ config I2C_RALINK
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depends on RALINK && !SOC_MT7621
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select OF_I2C
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+config I2C_MT7621
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+ tristate "MT7621/MT7628 I2C Controller"
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+ depends on RALINK && (SOC_MT7620 || SOC_MT7621)
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+ select OF_I2C
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+
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config HAVE_S3C2410_I2C
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bool
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help
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--- a/drivers/i2c/busses/Makefile
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+++ b/drivers/i2c/busses/Makefile
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@@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_PUV3) += i2c-puv3.o
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obj-$(CONFIG_I2C_PXA) += i2c-pxa.o
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obj-$(CONFIG_I2C_PXA_PCI) += i2c-pxa-pci.o
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obj-$(CONFIG_I2C_RALINK) += i2c-ralink.o
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+obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
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obj-$(CONFIG_I2C_QUP) += i2c-qup.o
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obj-$(CONFIG_I2C_RIIC) += i2c-riic.o
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obj-$(CONFIG_I2C_RK3X) += i2c-rk3x.o
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--- /dev/null
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+++ b/drivers/i2c/busses/i2c-mt7621.c
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@@ -0,0 +1,433 @@
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+/*
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+ * drivers/i2c/busses/i2c-mt7621.c
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+ *
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+ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
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+ * Copyright (C) 2016 Michael Lee <igvtee@gmail.com>
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+ *
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+ * Improve driver for i2cdetect from i2c-tools to detect i2c devices on the bus.
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+ * (C) 2014 Sittisak <sittisaks@hotmail.com>
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+ *
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+ * This software is licensed under the terms of the GNU General Public
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+ * License version 2, as published by the Free Software Foundation, and
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+ * may be copied, distributed, and modified under those terms.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ */
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+
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+#include <linux/interrupt.h>
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/reset.h>
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+#include <linux/delay.h>
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+#include <linux/slab.h>
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+#include <linux/init.h>
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+#include <linux/errno.h>
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+#include <linux/platform_device.h>
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+#include <linux/of_platform.h>
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+#include <linux/i2c.h>
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+#include <linux/io.h>
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+#include <linux/err.h>
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+#include <linux/clk.h>
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+
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+#define REG_SM0CFG0 0x08
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+#define REG_SM0DOUT 0x10
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+#define REG_SM0DIN 0x14
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+#define REG_SM0ST 0x18
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+#define REG_SM0AUTO 0x1C
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+#define REG_SM0CFG1 0x20
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+#define REG_SM0CFG2 0x28
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+#define REG_SM0CTL0 0x40
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+#define REG_SM0CTL1 0x44
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+#define REG_SM0D0 0x50
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+#define REG_SM0D1 0x54
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+#define REG_PINTEN 0x5C
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+#define REG_PINTST 0x60
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+#define REG_PINTCL 0x64
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+
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+/* REG_SM0CFG0 */
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+#define I2C_DEVADDR_MASK 0x7f
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+
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+/* REG_SM0ST */
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+#define I2C_DATARDY BIT(2)
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+#define I2C_SDOEMPTY BIT(1)
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+#define I2C_BUSY BIT(0)
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+
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+/* REG_SM0AUTO */
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+#define READ_CMD BIT(0)
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+
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+/* REG_SM0CFG1 */
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+#define BYTECNT_MAX 64
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+#define SET_BYTECNT(x) (x - 1)
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+
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+/* REG_SM0CFG2 */
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+#define AUTOMODE_EN BIT(0)
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+
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+/* REG_SM0CTL0 */
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+#define ODRAIN_HIGH_SM0 BIT(31)
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+#define VSYNC_SHIFT 28
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+#define VSYNC_MASK 0x3
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+#define VSYNC_PULSE (0x1 << VSYNC_SHIFT)
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+#define VSYNC_RISING (0x2 << VSYNC_SHIFT)
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+#define CLK_DIV_SHIFT 16
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+#define CLK_DIV_MASK 0xfff
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+#define DEG_CNT_SHIFT 8
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+#define DEG_CNT_MASK 0xff
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+#define WAIT_HIGH BIT(6)
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+#define DEG_EN BIT(5)
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+#define CS_STATUA BIT(4)
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+#define SCL_STATUS BIT(3)
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+#define SDA_STATUS BIT(2)
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+#define SM0_EN BIT(1)
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+#define SCL_STRECH BIT(0)
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+
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+/* REG_SM0CTL1 */
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+#define ACK_SHIFT 16
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+#define ACK_MASK 0xff
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+#define PGLEN_SHIFT 8
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+#define PGLEN_MASK 0x7
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+#define SM0_MODE_SHIFT 4
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+#define SM0_MODE_MASK 0x7
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+#define SM0_MODE_START 0x1
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+#define SM0_MODE_WRITE 0x2
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+#define SM0_MODE_STOP 0x3
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+#define SM0_MODE_READ_NACK 0x4
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+#define SM0_MODE_READ_ACK 0x5
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+#define SM0_TRI_BUSY BIT(0)
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+
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+/* timeout waiting for I2C devices to respond (clock streching) */
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+#define TIMEOUT_MS 1000
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+#define DELAY_INTERVAL_US 100
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+
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+struct mtk_i2c {
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+ void __iomem *base;
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+ struct clk *clk;
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+ struct device *dev;
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+ struct i2c_adapter adap;
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+ u32 cur_clk;
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+ u32 clk_div;
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+ u32 flags;
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+};
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+
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+static void mtk_i2c_w32(struct mtk_i2c *i2c, u32 val, unsigned reg)
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+{
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+ iowrite32(val, i2c->base + reg);
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+}
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+
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+static u32 mtk_i2c_r32(struct mtk_i2c *i2c, unsigned reg)
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+{
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+ return ioread32(i2c->base + reg);
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+}
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+
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+static int poll_down_timeout(void __iomem *addr, u32 mask)
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+{
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+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
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+
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+ do {
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+ if (!(readl_relaxed(addr) & mask))
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+ return 0;
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+
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+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
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+ } while (time_before(jiffies, timeout));
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+
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+ return (readl_relaxed(addr) & mask) ? -EAGAIN : 0;
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+}
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+
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+static int mtk_i2c_wait_idle(struct mtk_i2c *i2c)
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+{
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+ int ret;
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+
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+ ret = poll_down_timeout(i2c->base + REG_SM0ST, I2C_BUSY);
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+ if (ret < 0)
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+ dev_dbg(i2c->dev, "idle err(%d)\n", ret);
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+
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+ return ret;
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+}
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+
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+static int poll_up_timeout(void __iomem *addr, u32 mask)
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+{
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+ unsigned long timeout = jiffies + msecs_to_jiffies(TIMEOUT_MS);
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+ u32 status;
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+
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+ do {
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+ status = readl_relaxed(addr);
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+ if (status & mask)
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+ return 0;
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+ usleep_range(DELAY_INTERVAL_US, DELAY_INTERVAL_US + 50);
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+ } while (time_before(jiffies, timeout));
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+
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+ return -ETIMEDOUT;
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+}
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+
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+static int mtk_i2c_wait_rx_done(struct mtk_i2c *i2c)
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+{
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+ int ret;
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+
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+ ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_DATARDY);
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+ if (ret < 0)
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+ dev_dbg(i2c->dev, "rx err(%d)\n", ret);
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+
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+ return ret;
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+}
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+
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+static int mtk_i2c_wait_tx_done(struct mtk_i2c *i2c)
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+{
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+ int ret;
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+
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+ ret = poll_up_timeout(i2c->base + REG_SM0ST, I2C_SDOEMPTY);
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+ if (ret < 0)
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+ dev_dbg(i2c->dev, "tx err(%d)\n", ret);
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+
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+ return ret;
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+}
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+
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+static void mtk_i2c_reset(struct mtk_i2c *i2c)
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+{
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+ u32 reg;
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+ device_reset(i2c->adap.dev.parent);
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+ barrier();
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+
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+ /* ctrl0 */
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+ reg = ODRAIN_HIGH_SM0 | VSYNC_PULSE | (i2c->clk_div << CLK_DIV_SHIFT) |
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+ WAIT_HIGH | SM0_EN;
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+ mtk_i2c_w32(i2c, reg, REG_SM0CTL0);
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+
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+ /* auto mode */
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+ mtk_i2c_w32(i2c, AUTOMODE_EN, REG_SM0CFG2);
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+}
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+
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+static void mtk_i2c_dump_reg(struct mtk_i2c *i2c)
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+{
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+ dev_dbg(i2c->dev, "cfg0 %08x, dout %08x, din %08x, " \
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+ "status %08x, auto %08x, cfg1 %08x, " \
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+ "cfg2 %08x, ctl0 %08x, ctl1 %08x\n",
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+ mtk_i2c_r32(i2c, REG_SM0CFG0),
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+ mtk_i2c_r32(i2c, REG_SM0DOUT),
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+ mtk_i2c_r32(i2c, REG_SM0DIN),
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+ mtk_i2c_r32(i2c, REG_SM0ST),
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+ mtk_i2c_r32(i2c, REG_SM0AUTO),
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+ mtk_i2c_r32(i2c, REG_SM0CFG1),
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+ mtk_i2c_r32(i2c, REG_SM0CFG2),
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+ mtk_i2c_r32(i2c, REG_SM0CTL0),
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+ mtk_i2c_r32(i2c, REG_SM0CTL1));
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+}
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+
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+static int mtk_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
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+ int num)
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+{
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+ struct mtk_i2c *i2c;
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+ struct i2c_msg *pmsg;
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+ int i, j, ret;
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+ u32 cmd;
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+
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+ i2c = i2c_get_adapdata(adap);
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+
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+ for (i = 0; i < num; i++) {
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+ pmsg = &msgs[i];
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+ cmd = 0;
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+
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+ dev_dbg(i2c->dev, "addr: 0x%x, len: %d, flags: 0x%x\n",
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+ pmsg->addr, pmsg->len, pmsg->flags);
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+
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+ /* wait hardware idle */
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+ if ((ret = mtk_i2c_wait_idle(i2c)))
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+ goto err_timeout;
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+
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+ if (pmsg->flags & I2C_M_TEN) {
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+ dev_dbg(i2c->dev, "10 bits addr not supported\n");
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+ return -EINVAL;
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+ } else {
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+ /* 7 bits address */
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+ mtk_i2c_w32(i2c, pmsg->addr & I2C_DEVADDR_MASK,
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+ REG_SM0CFG0);
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+ }
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+
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+ /* buffer length */
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+ if (pmsg->len == 0) {
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+ dev_dbg(i2c->dev, "length is 0\n");
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+ return -EINVAL;
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+ } else
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+ mtk_i2c_w32(i2c, SET_BYTECNT(pmsg->len),
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+ REG_SM0CFG1);
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+
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+ j = 0;
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+ if (pmsg->flags & I2C_M_RD) {
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+ cmd |= READ_CMD;
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+ /* start transfer */
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+ barrier();
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+ mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
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+ do {
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+ /* wait */
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+ if ((ret = mtk_i2c_wait_rx_done(i2c)))
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+ goto err_timeout;
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+ /* read data */
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+ if (pmsg->len)
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+ pmsg->buf[j] = mtk_i2c_r32(i2c,
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+ REG_SM0DIN);
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+ j++;
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+ } while (j < pmsg->len);
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+ } else {
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+ do {
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+ /* write data */
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+ if (pmsg->len)
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+ mtk_i2c_w32(i2c, pmsg->buf[j],
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+ REG_SM0DOUT);
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+ /* start transfer */
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+ if (j == 0) {
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+ barrier();
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+ mtk_i2c_w32(i2c, cmd, REG_SM0AUTO);
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+ }
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+ /* wait */
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+ if ((ret = mtk_i2c_wait_tx_done(i2c)))
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+ goto err_timeout;
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+ j++;
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+ } while (j < pmsg->len);
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+ }
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+ }
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+ /* the return value is number of executed messages */
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+ ret = i;
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+
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+ return ret;
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+
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+err_timeout:
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+ mtk_i2c_dump_reg(i2c);
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+ mtk_i2c_reset(i2c);
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+ return ret;
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+}
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+
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+static u32 mtk_i2c_func(struct i2c_adapter *a)
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+{
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+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
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+}
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+
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+static const struct i2c_algorithm mtk_i2c_algo = {
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+ .master_xfer = mtk_i2c_master_xfer,
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+ .functionality = mtk_i2c_func,
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+};
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+
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+static const struct of_device_id i2c_mtk_dt_ids[] = {
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+ { .compatible = "mediatek,mt7621-i2c" },
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+ { /* sentinel */ }
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+};
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+
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+MODULE_DEVICE_TABLE(of, i2c_mtk_dt_ids);
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+
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+static struct i2c_adapter_quirks mtk_i2c_quirks = {
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+ .max_write_len = BYTECNT_MAX,
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+ .max_read_len = BYTECNT_MAX,
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+};
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+
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+static void mtk_i2c_init(struct mtk_i2c *i2c)
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+{
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+ i2c->clk_div = clk_get_rate(i2c->clk) / i2c->cur_clk;
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+ if (i2c->clk_div > CLK_DIV_MASK)
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+ i2c->clk_div = CLK_DIV_MASK;
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+
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+ mtk_i2c_reset(i2c);
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+}
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+
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+static int mtk_i2c_probe(struct platform_device *pdev)
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+{
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+ struct resource *res;
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+ struct mtk_i2c *i2c;
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+ struct i2c_adapter *adap;
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+ const struct of_device_id *match;
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+ int ret;
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+
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+ match = of_match_device(i2c_mtk_dt_ids, &pdev->dev);
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ if (!res) {
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+ dev_err(&pdev->dev, "no memory resource found\n");
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+ return -ENODEV;
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+ }
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+
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+ i2c = devm_kzalloc(&pdev->dev, sizeof(struct mtk_i2c), GFP_KERNEL);
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+ if (!i2c) {
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+ dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
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+ return -ENOMEM;
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+ }
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+
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+ i2c->base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(i2c->base))
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+ return PTR_ERR(i2c->base);
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+
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+ i2c->clk = devm_clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(i2c->clk)) {
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+ dev_err(&pdev->dev, "no clock defined\n");
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+ return -ENODEV;
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+ }
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+ clk_prepare_enable(i2c->clk);
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+ i2c->dev = &pdev->dev;
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+
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+ if (of_property_read_u32(pdev->dev.of_node,
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+ "clock-frequency", &i2c->cur_clk))
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+ i2c->cur_clk = 100000;
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+
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+ adap = &i2c->adap;
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+ adap->owner = THIS_MODULE;
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+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
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+ adap->algo = &mtk_i2c_algo;
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+ adap->retries = 3;
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+ adap->dev.parent = &pdev->dev;
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+ i2c_set_adapdata(adap, i2c);
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+ adap->dev.of_node = pdev->dev.of_node;
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+ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
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+ adap->quirks = &mtk_i2c_quirks;
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+
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+ platform_set_drvdata(pdev, i2c);
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+
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+ mtk_i2c_init(i2c);
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+
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+ ret = i2c_add_adapter(adap);
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+ if (ret < 0) {
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+ dev_err(&pdev->dev, "failed to add adapter\n");
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+ clk_disable_unprepare(i2c->clk);
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+ return ret;
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+ }
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+
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+ dev_info(&pdev->dev, "clock %uKHz, re-start not support\n",
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+ i2c->cur_clk/1000);
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+
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+ return ret;
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+}
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+
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+static int mtk_i2c_remove(struct platform_device *pdev)
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+{
|
|
+ struct mtk_i2c *i2c = platform_get_drvdata(pdev);
|
|
+
|
|
+ i2c_del_adapter(&i2c->adap);
|
|
+ clk_disable_unprepare(i2c->clk);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct platform_driver mtk_i2c_driver = {
|
|
+ .probe = mtk_i2c_probe,
|
|
+ .remove = mtk_i2c_remove,
|
|
+ .driver = {
|
|
+ .owner = THIS_MODULE,
|
|
+ .name = "i2c-mt7621",
|
|
+ .of_match_table = i2c_mtk_dt_ids,
|
|
+ },
|
|
+};
|
|
+
|
|
+static int __init i2c_mtk_init (void)
|
|
+{
|
|
+ return platform_driver_register(&mtk_i2c_driver);
|
|
+}
|
|
+subsys_initcall(i2c_mtk_init);
|
|
+
|
|
+static void __exit i2c_mtk_exit (void)
|
|
+{
|
|
+ platform_driver_unregister(&mtk_i2c_driver);
|
|
+}
|
|
+module_exit(i2c_mtk_exit);
|
|
+
|
|
+MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
|
|
+MODULE_DESCRIPTION("MT7621 I2c host driver");
|
|
+MODULE_LICENSE("GPL");
|
|
+MODULE_ALIAS("platform:MT7621-I2C");
|