1020 lines
33 KiB
C
1020 lines
33 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2010 Ralph Hempel <ralph.hempel@lantiq.com>
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* Copyright (C) 2009 Mohammad Firdaus
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*/
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/*!
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\defgroup IFX_DEU IFX_DEU_DRIVERS
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\ingroup API
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\brief ifx DEU driver module
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*/
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/*!
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\file ifxmips_aes.c
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\ingroup IFX_DEU
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\brief AES Encryption Driver main file
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*/
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/*!
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\defgroup IFX_AES_FUNCTIONS IFX_AES_FUNCTIONS
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\ingroup IFX_DEU
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\brief IFX AES driver Functions
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*/
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/* Project Header Files */
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include <linux/crypto.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <asm/byteorder.h>
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#include <crypto/algapi.h>
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#include "ifxmips_deu.h"
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/* DMA related header and variables */
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#ifdef CONFIG_CRYPTO_DEV_DMA
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#include "ifxmips_deu_dma.h"
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#include <asm/ifx/irq.h>
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#include <asm/ifx/ifx_dma_core.h>
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extern _ifx_deu_device ifx_deu[1];
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extern u32 *aes_buff_in;
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extern u32 *aes_buff_out;
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#ifndef CONFIG_CRYPTO_DEV_POLL_DMA
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#define CONFIG_CRYPTO_DEV_POLL_DMA
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#endif
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#endif /* CONFIG_CRYPTO_DEV_DMA */
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spinlock_t aes_lock;
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#define CRTCL_SECT_INIT spin_lock_init(&aes_lock)
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#define CRTCL_SECT_START spin_lock_irqsave(&aes_lock, flag)
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#define CRTCL_SECT_END spin_unlock_irqrestore(&aes_lock, flag)
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/* Definition of constants */
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#define AES_START IFX_AES_CON
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#define AES_MIN_KEY_SIZE 16
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#define AES_MAX_KEY_SIZE 32
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#define AES_BLOCK_SIZE 16
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#define CTR_RFC3686_NONCE_SIZE 4
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#define CTR_RFC3686_IV_SIZE 8
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#define CTR_RFC3686_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE)
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/* Function decleration */
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int aes_chip_init(void);
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u32 endian_swap(u32 input);
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u32 input_swap(u32 input);
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u32* memory_alignment(const u8 *arg, u32 *buff_alloc, int in_out, int nbytes);
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void aes_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
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void des_dma_memory_copy(u32 *outcopy, u32 *out_dma, u8 *out_arg, int nbytes);
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int aes_memory_allocate(int value);
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int des_memory_allocate(int value);
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void memory_release(u32 *addr);
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#ifndef CONFIG_CRYPTO_DEV_DMA
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extern void ifx_deu_aes (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,
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uint8_t *iv_arg, size_t nbytes, int encdec, int mode);
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#else
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extern void ifx_deu_aes_core (void *ctx_arg, uint8_t *out_arg, const uint8_t *in_arg,
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uint8_t *iv_arg, size_t nbytes, int encdec, int mode);
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#endif
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/* End of function decleration */
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struct aes_ctx {
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int key_length;
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u32 buf[AES_MAX_KEY_SIZE];
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u8 nonce[CTR_RFC3686_NONCE_SIZE];
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};
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extern int disable_deudma;
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/*! \fn int aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
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* \ingroup IFX_AES_FUNCTIONS
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* \brief sets the AES keys
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* \param tfm linux crypto algo transform
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* \param in_key input key
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* \param key_len key lengths of 16, 24 and 32 bytes supported
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* \return -EINVAL - bad key length, 0 - SUCCESS
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*/
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int aes_set_key (struct crypto_tfm *tfm, const u8 *in_key, unsigned int key_len)
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{
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struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
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u32 *flags = &tfm->crt_flags;
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DPRINTF(0, "ctx @%p, key_len %d\n", ctx, key_len);
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if (key_len != 16 && key_len != 24 && key_len != 32) {
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*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
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return -EINVAL;
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}
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ctx->key_length = key_len;
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memcpy ((u8 *) (ctx->buf), in_key, key_len);
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return 0;
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}
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#ifndef CONFIG_CRYPTO_DEV_DMA
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/*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)
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* \ingroup IFX_AES_FUNCTIONS
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* \brief main interface to AES hardware
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* \param ctx_arg crypto algo context
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* \param out_arg output bytestream
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* \param in_arg input bytestream
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* \param iv_arg initialization vector
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* \param nbytes length of bytestream
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* \param encdec 1 for encrypt; 0 for decrypt
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* \param mode operation mode such as ebc, cbc, ctr
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*
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*/
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void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
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u8 *iv_arg, size_t nbytes, int encdec, int mode)
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#else
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/*! \fn void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, size_t nbytes, int encdec, int mode)
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* \ingroup IFX_AES_FUNCTIONS
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* \brief main interface to AES hardware
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* \param ctx_arg crypto algo context
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* \param out_arg output bytestream
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* \param in_arg input bytestream
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* \param iv_arg initialization vector
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* \param nbytes length of bytestream
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* \param encdec 1 for encrypt; 0 for decrypt
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* \param mode operation mode such as ebc, cbc, ctr
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*
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*/
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void ifx_deu_aes_core (void *ctx_arg, u8 *out_arg, const u8 *in_arg,
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u8 *iv_arg, size_t nbytes, int encdec, int mode)
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#endif
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{
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/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
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volatile struct aes_t *aes = (volatile struct aes_t *) AES_START;
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struct aes_ctx *ctx = (struct aes_ctx *)ctx_arg;
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u32 *in_key = ctx->buf;
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ulong flag;
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/*~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
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int key_len = ctx->key_length;
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#ifndef CONFIG_CRYPTO_DEV_DMA
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int i = 0;
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int byte_cnt = nbytes;
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#else
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volatile struct deu_dma_t *dma = (struct deu_dma_t *) IFX_DEU_DMA_CON;
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struct dma_device_info *dma_device = ifx_deu[0].dma_device;
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//deu_drv_priv_t *deu_priv = (deu_drv_priv_t *)dma_device->priv;
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int wlen = 0;
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u32 *outcopy = NULL;
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u32 *dword_mem_aligned_in = NULL;
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#ifdef CONFIG_CRYPTO_DEV_POLL_DMA
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u32 timeout = 0;
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u32 *out_dma = NULL;
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#endif
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#endif
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DPRINTF(0, "ctx @%p, mode %d, encdec %d\n", ctx, mode, encdec);
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CRTCL_SECT_START;
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/* 128, 192 or 256 bit key length */
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aes->controlr.K = key_len / 8 - 2;
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if (key_len == 128 / 8) {
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aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
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aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
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aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
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aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
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}
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else if (key_len == 192 / 8) {
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aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
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aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
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aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
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aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
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aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
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aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
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}
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else if (key_len == 256 / 8) {
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aes->K7R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 0));
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aes->K6R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 1));
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aes->K5R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 2));
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aes->K4R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 3));
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aes->K3R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 4));
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aes->K2R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 5));
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aes->K1R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 6));
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aes->K0R = DEU_ENDIAN_SWAP(*((u32 *) in_key + 7));
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}
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else {
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printk (KERN_ERR "[%s %s %d]: Invalid key_len : %d\n", __FILE__, __func__, __LINE__, key_len);
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CRTCL_SECT_END;
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return;// -EINVAL;
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}
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/* let HW pre-process DEcryption key in any case (even if
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ENcryption is used). Key Valid (KV) bit is then only
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checked in decryption routine! */
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aes->controlr.PNK = 1;
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#ifdef CONFIG_CRYPTO_DEV_DMA
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while (aes->controlr.BUS) {
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// this will not take long
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}
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AES_DMA_MISC_CONFIG();
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#endif
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aes->controlr.E_D = !encdec; /* encryption */
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aes->controlr.O = mode; /* 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR */
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aes->controlr.SM = 1; /* start after writing input register */
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aes->controlr.DAU = 0; /* Disable Automatic Update of init vector */
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aes->controlr.ARS = 1; /* Autostart Select - write to IHR */
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//aes->controlr.F = 128; //default; only for CFB and OFB modes; change only for customer-specific apps
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if (mode > 0) {
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aes->IV3R = DEU_ENDIAN_SWAP(*(u32 *) iv_arg);
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aes->IV2R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
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aes->IV1R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));
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aes->IV0R = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));
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};
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#ifndef CONFIG_CRYPTO_DEV_DMA
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i = 0;
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while (byte_cnt >= 16) {
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aes->ID3R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 0));
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aes->ID2R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 1));
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aes->ID1R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 2));
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aes->ID0R = INPUT_ENDIAN_SWAP(*((u32 *) in_arg + (i * 4) + 3)); /* start crypto */
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while (aes->controlr.BUS) {
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// this will not take long
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}
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*((volatile u32 *) out_arg + (i * 4) + 0) = aes->OD3R;
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*((volatile u32 *) out_arg + (i * 4) + 1) = aes->OD2R;
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*((volatile u32 *) out_arg + (i * 4) + 2) = aes->OD1R;
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*((volatile u32 *) out_arg + (i * 4) + 3) = aes->OD0R;
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i++;
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byte_cnt -= 16;
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}
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#else // dma
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/* Prepare Rx buf length used in dma psuedo interrupt */
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//deu_priv->deu_rx_buf = out_arg;
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//deu_priv->deu_rx_len = nbytes;
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/* memory alignment issue */
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dword_mem_aligned_in = (u32 *) DEU_DWORD_REORDERING(in_arg, aes_buff_in, BUFFER_IN, nbytes);
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dma->controlr.ALGO = 1; //AES
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dma->controlr.BS = 0;
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aes->controlr.DAU = 0;
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dma->controlr.EN = 1;
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while (aes->controlr.BUS) {
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// wait for AES to be ready
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};
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wlen = dma_device_write (dma_device, (u8 *)dword_mem_aligned_in, nbytes, NULL);
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if (wlen != nbytes) {
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dma->controlr.EN = 0;
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CRTCL_SECT_END;
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printk (KERN_ERR "[%s %s %d]: dma_device_write fail!\n", __FILE__, __func__, __LINE__);
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return; // -EINVAL;
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}
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WAIT_AES_DMA_READY();
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#ifdef CONFIG_CRYPTO_DEV_POLL_DMA
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outcopy = (u32 *) DEU_DWORD_REORDERING(out_arg, aes_buff_out, BUFFER_OUT, nbytes);
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// polling DMA rx channel
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while ((dma_device_read (dma_device, (u8 **) &out_dma, NULL)) == 0) {
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timeout++;
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if (timeout >= 333000) {
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dma->controlr.EN = 0;
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CRTCL_SECT_END;
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printk (KERN_ERR "[%s %s %d]: timeout!!\n", __FILE__, __func__, __LINE__);
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return; // -EINVAL;
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}
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}
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WAIT_AES_DMA_READY();
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AES_MEMORY_COPY(outcopy, out_dma, out_arg, nbytes);
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#else // not working at the moment..
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CRTCL_SECT_END;
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/* Sleep and wait for Rx finished */
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DEU_WAIT_EVENT(deu_priv->deu_thread_wait, DEU_EVENT, deu_priv->deu_event_flags);
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CRTCL_SECT_START;
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#endif
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#endif // dma
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//tc.chen : copy iv_arg back
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if (mode > 0) {
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*((u32 *) iv_arg) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg));
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*((u32 *) iv_arg + 1) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 1));
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*((u32 *) iv_arg + 2) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 2));
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*((u32 *) iv_arg + 3) = DEU_ENDIAN_SWAP(*((u32 *) iv_arg + 3));
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}
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CRTCL_SECT_END;
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}
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/*!
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* \fn int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
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* \ingroup IFX_AES_FUNCTIONS
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* \brief sets RFC3686 key
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* \param tfm linux crypto algo transform
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* \param in_key input key
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* \param key_len key lengths of 20, 28 and 36 bytes supported; last 4 bytes is nonce
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* \return 0 - SUCCESS
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* -EINVAL - bad key length
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*/
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int ctr_rfc3686_aes_set_key (struct crypto_tfm *tfm, const uint8_t *in_key, unsigned int key_len)
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{
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struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
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u32 *flags = &tfm->crt_flags;
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printk("ctr_rfc3686_aes_set_key in %s\n", __FILE__);
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memcpy(ctx->nonce, in_key + (key_len - CTR_RFC3686_NONCE_SIZE),
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CTR_RFC3686_NONCE_SIZE);
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key_len -= CTR_RFC3686_NONCE_SIZE; // remove 4 bytes of nonce
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if (key_len != 16 && key_len != 24 && key_len != 32) {
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*flags |= CRYPTO_TFM_RES_BAD_KEY_LEN;
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return -EINVAL;
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}
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ctx->key_length = key_len;
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memcpy ((u8 *) (ctx->buf), in_key, key_len);
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return 0;
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}
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/*! \fn void ifx_deu_aes (void *ctx_arg, u8 *out_arg, const u8 *in_arg, u8 *iv_arg, u32 nbytes, int encdec, int mode)
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* \ingroup IFX_AES_FUNCTIONS
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* \brief main interface with deu hardware in DMA mode
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* \param ctx_arg crypto algo context
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* \param out_arg output bytestream
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* \param in_arg input bytestream
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* \param iv_arg initialization vector
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* \param nbytes length of bytestream
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* \param encdec 1 for encrypt; 0 for decrypt
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* \param mode operation mode such as ebc, cbc, ctr
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*/
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#ifdef CONFIG_CRYPTO_DEV_DMA
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void ifx_deu_aes (void *ctx_arg, u8 * out_arg, const u8 * in_arg,
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u8 * iv_arg, u32 nbytes, int encdec, int mode)
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{
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u32 remain = nbytes;
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u32 inc;
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while (remain > 0)
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{
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if (remain >= DEU_MAX_PACKET_SIZE)
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{
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inc = DEU_MAX_PACKET_SIZE;
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}
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else
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{
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inc = remain;
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}
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remain -= inc;
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ifx_deu_aes_core(ctx_arg, out_arg, in_arg, iv_arg, inc, encdec, mode);
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out_arg += inc;
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in_arg += inc;
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}
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}
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#endif
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//definitions from linux/include/crypto.h:
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//#define CRYPTO_TFM_MODE_ECB 0x00000001
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//#define CRYPTO_TFM_MODE_CBC 0x00000002
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//#define CRYPTO_TFM_MODE_CFB 0x00000004
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//#define CRYPTO_TFM_MODE_CTR 0x00000008
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//#define CRYPTO_TFM_MODE_OFB 0x00000010 // not even defined
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//but hardware definition: 0 ECB 1 CBC 2 OFB 3 CFB 4 CTR
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/*! \fn void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
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* \ingroup IFX_AES_FUNCTIONS
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* \brief sets AES hardware to ECB mode
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* \param ctx crypto algo context
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* \param dst output bytestream
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* \param src input bytestream
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* \param iv initialization vector
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* \param nbytes length of bytestream
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* \param encdec 1 for encrypt; 0 for decrypt
|
|
* \param inplace not used
|
|
*/
|
|
void ifx_deu_aes_ecb (void *ctx, uint8_t *dst, const uint8_t *src,
|
|
uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
{
|
|
ifx_deu_aes (ctx, dst, src, NULL, nbytes, encdec, 0);
|
|
}
|
|
|
|
/*! \fn void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief sets AES hardware to CBC mode
|
|
* \param ctx crypto algo context
|
|
* \param dst output bytestream
|
|
* \param src input bytestream
|
|
* \param iv initialization vector
|
|
* \param nbytes length of bytestream
|
|
* \param encdec 1 for encrypt; 0 for decrypt
|
|
* \param inplace not used
|
|
*/
|
|
void ifx_deu_aes_cbc (void *ctx, uint8_t *dst, const uint8_t *src,
|
|
uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
{
|
|
ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 1);
|
|
}
|
|
|
|
/*! \fn void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief sets AES hardware to OFB mode
|
|
* \param ctx crypto algo context
|
|
* \param dst output bytestream
|
|
* \param src input bytestream
|
|
* \param iv initialization vector
|
|
* \param nbytes length of bytestream
|
|
* \param encdec 1 for encrypt; 0 for decrypt
|
|
* \param inplace not used
|
|
*/
|
|
void ifx_deu_aes_ofb (void *ctx, uint8_t *dst, const uint8_t *src,
|
|
uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
{
|
|
ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 2);
|
|
}
|
|
|
|
/*! \fn void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief sets AES hardware to CFB mode
|
|
* \param ctx crypto algo context
|
|
* \param dst output bytestream
|
|
* \param src input bytestream
|
|
* \param iv initialization vector
|
|
* \param nbytes length of bytestream
|
|
* \param encdec 1 for encrypt; 0 for decrypt
|
|
* \param inplace not used
|
|
*/
|
|
void ifx_deu_aes_cfb (void *ctx, uint8_t *dst, const uint8_t *src,
|
|
uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
{
|
|
ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 3);
|
|
}
|
|
|
|
/*! \fn void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src, uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief sets AES hardware to CTR mode
|
|
* \param ctx crypto algo context
|
|
* \param dst output bytestream
|
|
* \param src input bytestream
|
|
* \param iv initialization vector
|
|
* \param nbytes length of bytestream
|
|
* \param encdec 1 for encrypt; 0 for decrypt
|
|
* \param inplace not used
|
|
*/
|
|
void ifx_deu_aes_ctr (void *ctx, uint8_t *dst, const uint8_t *src,
|
|
uint8_t *iv, size_t nbytes, int encdec, int inplace)
|
|
{
|
|
ifx_deu_aes (ctx, dst, src, iv, nbytes, encdec, 4);
|
|
}
|
|
|
|
/*! \fn void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief encrypt AES_BLOCK_SIZE of data
|
|
* \param tfm linux crypto algo transform
|
|
* \param out output bytestream
|
|
* \param in input bytestream
|
|
*/
|
|
void aes_encrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
|
|
{
|
|
struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
|
|
CRYPTO_DIR_ENCRYPT, 0);
|
|
|
|
}
|
|
|
|
/*! \fn void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief decrypt AES_BLOCK_SIZE of data
|
|
* \param tfm linux crypto algo transform
|
|
* \param out output bytestream
|
|
* \param in input bytestream
|
|
*/
|
|
void aes_decrypt (struct crypto_tfm *tfm, uint8_t *out, const uint8_t *in)
|
|
{
|
|
struct aes_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
ifx_deu_aes (ctx, out, in, NULL, AES_BLOCK_SIZE,
|
|
CRYPTO_DIR_DECRYPT, 0);
|
|
}
|
|
|
|
/*
|
|
* \brief AES function mappings
|
|
*/
|
|
struct crypto_alg ifxdeu_aes_alg = {
|
|
.cra_name = "aes",
|
|
.cra_driver_name = "ifxdeu-aes",
|
|
.cra_flags = CRYPTO_ALG_TYPE_CIPHER,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct aes_ctx),
|
|
.cra_module = THIS_MODULE,
|
|
.cra_list = LIST_HEAD_INIT(ifxdeu_aes_alg.cra_list),
|
|
.cra_u = {
|
|
.cipher = {
|
|
.cia_min_keysize = AES_MIN_KEY_SIZE,
|
|
.cia_max_keysize = AES_MAX_KEY_SIZE,
|
|
.cia_setkey = aes_set_key,
|
|
.cia_encrypt = aes_encrypt,
|
|
.cia_decrypt = aes_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
/*! \fn int ecb_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief ECB AES encrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int ecb_aes_encrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
NULL, nbytes, CRYPTO_DIR_ENCRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*! \fn int ecb_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief ECB AES decrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int ecb_aes_decrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_ecb(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
NULL, nbytes, CRYPTO_DIR_DECRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* \brief AES function mappings
|
|
*/
|
|
struct crypto_alg ifxdeu_ecb_aes_alg = {
|
|
.cra_name = "ecb(aes)",
|
|
.cra_driver_name = "ifxdeu-ecb(aes)",
|
|
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct aes_ctx),
|
|
.cra_type = &crypto_blkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_list = LIST_HEAD_INIT(ifxdeu_ecb_aes_alg.cra_list),
|
|
.cra_u = {
|
|
.blkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.setkey = aes_set_key,
|
|
.encrypt = ecb_aes_encrypt,
|
|
.decrypt = ecb_aes_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
|
|
/*! \fn int cbc_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief CBC AES encrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int cbc_aes_encrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
u8 *iv = walk.iv;
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*! \fn int cbc_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief CBC AES decrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int cbc_aes_decrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
u8 *iv = walk.iv;
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_cbc(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* \brief AES function mappings
|
|
*/
|
|
struct crypto_alg ifxdeu_cbc_aes_alg = {
|
|
.cra_name = "cbc(aes)",
|
|
.cra_driver_name = "ifxdeu-cbc(aes)",
|
|
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct aes_ctx),
|
|
.cra_type = &crypto_blkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_list = LIST_HEAD_INIT(ifxdeu_cbc_aes_alg.cra_list),
|
|
.cra_u = {
|
|
.blkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.setkey = aes_set_key,
|
|
.encrypt = cbc_aes_encrypt,
|
|
.decrypt = cbc_aes_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
|
|
/*! \fn int ctr_basic_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief Counter mode AES encrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int ctr_basic_aes_encrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
u8 *iv = walk.iv;
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*! \fn int ctr_basic_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief Counter mode AES decrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int ctr_basic_aes_decrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
u8 *iv = walk.iv;
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* \brief AES function mappings
|
|
*/
|
|
struct crypto_alg ifxdeu_ctr_basic_aes_alg = {
|
|
.cra_name = "ctr(aes)",
|
|
.cra_driver_name = "ifxdeu-ctr(aes)",
|
|
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct aes_ctx),
|
|
.cra_type = &crypto_blkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_list = LIST_HEAD_INIT(ifxdeu_ctr_basic_aes_alg.cra_list),
|
|
.cra_u = {
|
|
.blkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
.setkey = aes_set_key,
|
|
.encrypt = ctr_basic_aes_encrypt,
|
|
.decrypt = ctr_basic_aes_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
|
|
/*! \fn int ctr_rfc3686_aes_encrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief Counter mode AES (rfc3686) encrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int ctr_rfc3686_aes_encrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
u8 rfc3686_iv[16];
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
/* set up counter block */
|
|
memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
|
|
memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
|
|
|
|
/* initialize counter portion of counter block */
|
|
*(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
|
|
cpu_to_be32(1);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
rfc3686_iv, nbytes, CRYPTO_DIR_ENCRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*! \fn int ctr_rfc3686_aes_decrypt(struct blkcipher_desc *desc, struct scatterlist *dst, struct scatterlist *src, unsigned int nbytes)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief Counter mode AES (rfc3686) decrypt using linux crypto blkcipher
|
|
* \param desc blkcipher descriptor
|
|
* \param dst output scatterlist
|
|
* \param src input scatterlist
|
|
* \param nbytes data size in bytes
|
|
* \return err
|
|
*/
|
|
int ctr_rfc3686_aes_decrypt(struct blkcipher_desc *desc,
|
|
struct scatterlist *dst, struct scatterlist *src,
|
|
unsigned int nbytes)
|
|
{
|
|
struct aes_ctx *ctx = crypto_blkcipher_ctx(desc->tfm);
|
|
struct blkcipher_walk walk;
|
|
int err;
|
|
u8 rfc3686_iv[16];
|
|
|
|
blkcipher_walk_init(&walk, dst, src, nbytes);
|
|
err = blkcipher_walk_virt(desc, &walk);
|
|
|
|
/* set up counter block */
|
|
memcpy(rfc3686_iv, ctx->nonce, CTR_RFC3686_NONCE_SIZE);
|
|
memcpy(rfc3686_iv + CTR_RFC3686_NONCE_SIZE, walk.iv, CTR_RFC3686_IV_SIZE);
|
|
|
|
/* initialize counter portion of counter block */
|
|
*(__be32 *)(rfc3686_iv + CTR_RFC3686_NONCE_SIZE + CTR_RFC3686_IV_SIZE) =
|
|
cpu_to_be32(1);
|
|
|
|
while ((nbytes = walk.nbytes)) {
|
|
nbytes -= (nbytes % AES_BLOCK_SIZE);
|
|
ifx_deu_aes_ctr(ctx, walk.dst.virt.addr, walk.src.virt.addr,
|
|
rfc3686_iv, nbytes, CRYPTO_DIR_DECRYPT, 0);
|
|
nbytes &= AES_BLOCK_SIZE - 1;
|
|
err = blkcipher_walk_done(desc, &walk, nbytes);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
/*
|
|
* \brief AES function mappings
|
|
*/
|
|
struct crypto_alg ifxdeu_ctr_rfc3686_aes_alg = {
|
|
.cra_name = "rfc3686(ctr(aes))",
|
|
.cra_driver_name = "ifxdeu-ctr-rfc3686(aes)",
|
|
.cra_flags = CRYPTO_ALG_TYPE_BLKCIPHER,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct aes_ctx),
|
|
.cra_type = &crypto_blkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_list = LIST_HEAD_INIT(ifxdeu_ctr_rfc3686_aes_alg.cra_list),
|
|
.cra_u = {
|
|
.blkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = CTR_RFC3686_MAX_KEY_SIZE,
|
|
.ivsize = CTR_RFC3686_IV_SIZE,
|
|
.setkey = ctr_rfc3686_aes_set_key,
|
|
.encrypt = ctr_rfc3686_aes_encrypt,
|
|
.decrypt = ctr_rfc3686_aes_decrypt,
|
|
}
|
|
}
|
|
};
|
|
|
|
|
|
/*! \fn int __init ifxdeu_init_aes (void)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief function to initialize AES driver
|
|
* \return ret
|
|
*/
|
|
int __init ifxdeu_init_aes (void)
|
|
{
|
|
int ret;
|
|
|
|
if ((ret = crypto_register_alg(&ifxdeu_aes_alg)))
|
|
goto aes_err;
|
|
|
|
if ((ret = crypto_register_alg(&ifxdeu_ecb_aes_alg)))
|
|
goto ecb_aes_err;
|
|
|
|
if ((ret = crypto_register_alg(&ifxdeu_cbc_aes_alg)))
|
|
goto cbc_aes_err;
|
|
|
|
if ((ret = crypto_register_alg(&ifxdeu_ctr_basic_aes_alg)))
|
|
goto ctr_basic_aes_err;
|
|
|
|
if ((ret = crypto_register_alg(&ifxdeu_ctr_rfc3686_aes_alg)))
|
|
goto ctr_rfc3686_aes_err;
|
|
|
|
aes_chip_init ();
|
|
|
|
CRTCL_SECT_INIT;
|
|
|
|
#ifdef CONFIG_CRYPTO_DEV_DMA
|
|
if (ALLOCATE_MEMORY(BUFFER_IN, AES_ALGO) < 0) {
|
|
printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
|
|
goto ctr_rfc3686_aes_err;
|
|
}
|
|
if (ALLOCATE_MEMORY(BUFFER_OUT, AES_ALGO) < 0) {
|
|
printk(KERN_ERR "[%s %s %d]: malloc memory fail!\n", __FILE__, __func__, __LINE__);
|
|
goto ctr_rfc3686_aes_err;
|
|
}
|
|
#endif
|
|
|
|
printk (KERN_NOTICE "IFX DEU AES initialized %s.\n", disable_deudma ? "" : " (DMA)");
|
|
return ret;
|
|
|
|
ctr_rfc3686_aes_err:
|
|
crypto_unregister_alg(&ifxdeu_ctr_rfc3686_aes_alg);
|
|
printk (KERN_ERR "IFX ctr_rfc3686_aes initialization failed!\n");
|
|
return ret;
|
|
ctr_basic_aes_err:
|
|
crypto_unregister_alg(&ifxdeu_ctr_basic_aes_alg);
|
|
printk (KERN_ERR "IFX ctr_basic_aes initialization failed!\n");
|
|
return ret;
|
|
cbc_aes_err:
|
|
crypto_unregister_alg(&ifxdeu_cbc_aes_alg);
|
|
printk (KERN_ERR "IFX cbc_aes initialization failed!\n");
|
|
return ret;
|
|
ecb_aes_err:
|
|
crypto_unregister_alg(&ifxdeu_ecb_aes_alg);
|
|
printk (KERN_ERR "IFX aes initialization failed!\n");
|
|
return ret;
|
|
aes_err:
|
|
printk(KERN_ERR "IFX DEU AES initialization failed!\n");
|
|
return ret;
|
|
}
|
|
|
|
/*! \fn void __exit ifxdeu_fini_aes (void)
|
|
* \ingroup IFX_AES_FUNCTIONS
|
|
* \brief unregister aes driver
|
|
*/
|
|
void __exit ifxdeu_fini_aes (void)
|
|
{
|
|
crypto_unregister_alg (&ifxdeu_aes_alg);
|
|
crypto_unregister_alg (&ifxdeu_ecb_aes_alg);
|
|
crypto_unregister_alg (&ifxdeu_cbc_aes_alg);
|
|
crypto_unregister_alg (&ifxdeu_ctr_basic_aes_alg);
|
|
crypto_unregister_alg (&ifxdeu_ctr_rfc3686_aes_alg);
|
|
|
|
#ifdef CONFIG_CRYPTO_DEV_DMA
|
|
FREE_MEMORY(aes_buff_in);
|
|
FREE_MEMORY(aes_buff_out);
|
|
#endif
|
|
|
|
}
|
|
|