dfcd340721
Add patches from Hauke adding linux 3.0 compatibility. Signed-off-by: Jonas Gorski <jonas.gorski+openwrt@gmail.com> SVN-Revision: 27187
51 lines
1.5 KiB
Diff
51 lines
1.5 KiB
Diff
--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -742,6 +742,39 @@ static void ath9k_hw_init_pll(struct ath
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REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
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AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
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udelay(1000);
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+ } else if (AR_SREV_9330(ah)) {
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+ u32 ddr_dpll2, pll_control2, kd;
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+
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+ if (ah->is_clk_25mhz) {
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+ ddr_dpll2 = 0x18e82f01;
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+ pll_control2 = 0xe04a3d;
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+ kd = 0x1d;
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+ } else {
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+ ddr_dpll2 = 0x19e82f01;
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+ pll_control2 = 0x886666;
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+ kd = 0x3d;
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+ }
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+
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+ /* program DDR PLL ki and kd value */
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+ REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
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+
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+ /* program DDR PLL phase_shift */
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+ REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
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+ AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
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+
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+ REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
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+ udelay(1000);
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+
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+ /* program refdiv, nint, frac to RTC register */
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+ REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
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+
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+ /* program BB PLL kd and ki value */
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+ REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
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+ REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
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+
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+ /* program BB PLL phase_shift */
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+ REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
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+ AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
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} else if (AR_SREV_9340(ah)) {
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u32 regval, pll2_divint, pll2_divfrac, refdiv;
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@@ -783,7 +816,7 @@ static void ath9k_hw_init_pll(struct ath
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REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
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- if (AR_SREV_9485(ah) || AR_SREV_9340(ah))
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+ if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
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udelay(1000);
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/* Switch the core clock for ar9271 to 117Mhz */
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