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openwrtv4/target/linux/oxnas/patches-4.4/0074-mtd-nand-import-nand_hw_control_init.patch
Victor Shyba d6c831e0e5 generic: mtd: backport SPI_NOR_HAS_LOCK 
This flag was added to 4.9 with upstream commit
76a4707de5e18dc32d9cb4e990686140c5664a15.

Signed-off-by: Victor Shyba <victor1984@riseup.net>
[refresh and adjust platform patches, fix commit message]
Signed-off-by: Mathias Kresin <dev@kresin.me>
2017-01-03 19:58:00 +01:00

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5.9 KiB
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From d45bc58dd3bdcaabc1d7d8d9b0b8dee826635cc6 Mon Sep 17 00:00:00 2001
From: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Date: Wed, 27 Jul 2016 11:23:52 +0200
Subject: [PATCH] mtd: nand: import nand_hw_control_init()
The code to initialize a struct nand_hw_control is duplicated across
several drivers. Factorize it using an inline function.
Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
---
drivers/mtd/nand/bf5xx_nand.c | 3 +--
drivers/mtd/nand/brcmnand/brcmnand.c | 3 +--
drivers/mtd/nand/docg4.c | 3 +--
drivers/mtd/nand/fsl_elbc_nand.c | 3 +--
drivers/mtd/nand/fsl_ifc_nand.c | 3 +--
drivers/mtd/nand/jz4780_nand.c | 3 +--
drivers/mtd/nand/nand_base.c | 3 +--
drivers/mtd/nand/ndfc.c | 3 +--
drivers/mtd/nand/pxa3xx_nand.c | 3 +--
drivers/mtd/nand/qcom_nandc.c | 3 +--
drivers/mtd/nand/s3c2410.c | 3 +--
drivers/mtd/nand/sunxi_nand.c | 3 +--
drivers/mtd/nand/txx9ndfmc.c | 3 +--
include/linux/mtd/nand.h | 7 +++++++
14 files changed, 20 insertions(+), 26 deletions(-)
--- a/drivers/mtd/nand/bf5xx_nand.c
+++ b/drivers/mtd/nand/bf5xx_nand.c
@@ -748,8 +748,7 @@ static int bf5xx_nand_probe(struct platf
platform_set_drvdata(pdev, info);
- spin_lock_init(&info->controller.lock);
- init_waitqueue_head(&info->controller.wq);
+ nand_hw_control_init(&info->controller);
info->device = &pdev->dev;
info->platform = plat;
--- a/drivers/mtd/nand/brcmnand/brcmnand.c
+++ b/drivers/mtd/nand/brcmnand/brcmnand.c
@@ -2156,8 +2156,7 @@ int brcmnand_probe(struct platform_devic
init_completion(&ctrl->done);
init_completion(&ctrl->dma_done);
- spin_lock_init(&ctrl->controller.lock);
- init_waitqueue_head(&ctrl->controller.wq);
+ nand_hw_control_init(&ctrl->controller);
INIT_LIST_HEAD(&ctrl->host_list);
/* NAND register range */
--- a/drivers/mtd/nand/docg4.c
+++ b/drivers/mtd/nand/docg4.c
@@ -1227,8 +1227,7 @@ static void __init init_mtd_structs(stru
nand->options = NAND_BUSWIDTH_16 | NAND_NO_SUBPAGE_WRITE;
nand->IO_ADDR_R = nand->IO_ADDR_W = doc->virtadr + DOC_IOSPACE_DATA;
nand->controller = &nand->hwcontrol;
- spin_lock_init(&nand->controller->lock);
- init_waitqueue_head(&nand->controller->wq);
+ nand_hw_control_init(nand->controller);
/* methods */
nand->cmdfunc = docg4_command;
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -866,8 +866,7 @@ static int fsl_elbc_nand_probe(struct pl
}
elbc_fcm_ctrl->counter++;
- spin_lock_init(&elbc_fcm_ctrl->controller.lock);
- init_waitqueue_head(&elbc_fcm_ctrl->controller.wq);
+ nand_hw_control_init(&elbc_fcm_ctrl->controller);
fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
} else {
elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -1073,8 +1073,7 @@ static int fsl_ifc_nand_probe(struct pla
ifc_nand_ctrl->addr = NULL;
fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
- spin_lock_init(&ifc_nand_ctrl->controller.lock);
- init_waitqueue_head(&ifc_nand_ctrl->controller.wq);
+ nand_hw_control_init(&ifc_nand_ctrl->controller);
} else {
ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
}
--- a/drivers/mtd/nand/nand_base.c
+++ b/drivers/mtd/nand/nand_base.c
@@ -3202,8 +3202,7 @@ static void nand_set_defaults(struct nan
if (!chip->controller) {
chip->controller = &chip->hwcontrol;
- spin_lock_init(&chip->controller->lock);
- init_waitqueue_head(&chip->controller->wq);
+ nand_hw_control_init(chip->controller);
}
}
--- a/drivers/mtd/nand/ndfc.c
+++ b/drivers/mtd/nand/ndfc.c
@@ -220,8 +220,7 @@ static int ndfc_probe(struct platform_de
ndfc = &ndfc_ctrl[cs];
ndfc->chip_select = cs;
- spin_lock_init(&ndfc->ndfc_control.lock);
- init_waitqueue_head(&ndfc->ndfc_control.wq);
+ nand_hw_control_init(&ndfc->ndfc_control);
ndfc->ofdev = ofdev;
dev_set_drvdata(&ofdev->dev, ndfc);
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1739,8 +1739,7 @@ static int alloc_nand_resource(struct pl
chip->cmdfunc = nand_cmdfunc;
}
- spin_lock_init(&chip->controller->lock);
- init_waitqueue_head(&chip->controller->wq);
+ nand_hw_control_init(chip->controller);
info->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(info->clk)) {
dev_err(&pdev->dev, "failed to get nand clock\n");
--- a/drivers/mtd/nand/s3c2410.c
+++ b/drivers/mtd/nand/s3c2410.c
@@ -955,8 +955,7 @@ static int s3c24xx_nand_probe(struct pla
platform_set_drvdata(pdev, info);
- spin_lock_init(&info->controller.lock);
- init_waitqueue_head(&info->controller.wq);
+ nand_hw_control_init(&info->controller);
/* get the clock source and enable it */
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -1426,8 +1426,7 @@ static int sunxi_nfc_probe(struct platfo
return -ENOMEM;
nfc->dev = dev;
- spin_lock_init(&nfc->controller.lock);
- init_waitqueue_head(&nfc->controller.wq);
+ nand_hw_control_init(&nfc->controller);
INIT_LIST_HEAD(&nfc->chips);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--- a/drivers/mtd/nand/txx9ndfmc.c
+++ b/drivers/mtd/nand/txx9ndfmc.c
@@ -304,8 +304,7 @@ static int __init txx9ndfmc_probe(struct
dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n",
(gbusclk + 500000) / 1000000, hold, spw);
- spin_lock_init(&drvdata->hw_control.lock);
- init_waitqueue_head(&drvdata->hw_control.wq);
+ nand_hw_control_init(&drvdata->hw_control);
platform_set_drvdata(dev, drvdata);
txx9ndfmc_initialize(dev);
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -461,6 +461,13 @@ struct nand_hw_control {
wait_queue_head_t wq;
};
+static inline void nand_hw_control_init(struct nand_hw_control *nfc)
+{
+ nfc->active = NULL;
+ spin_lock_init(&nfc->lock);
+ init_waitqueue_head(&nfc->wq);
+}
+
/**
* struct nand_ecc_ctrl - Control structure for ECC
* @mode: ECC mode
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