672a8cd6ba
Changes include PCI fixes and various upstream pending patches. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 38624
60 lines
3.9 KiB
Diff
60 lines
3.9 KiB
Diff
From 64990a431469a58b2949aca5be9d69e220d53892 Mon Sep 17 00:00:00 2001
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From: Nicolin Chen <b42378@freescale.com>
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Date: Fri, 23 Aug 2013 19:20:34 +0800
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Subject: [PATCH] ARM: imx6q: Add pll4_audio_div to clock tree
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There's a pll4_audio_div clock, an extra divider for pll4, missing
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in current clock tree, thus add it.
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Signed-off-by: Nicolin Chen <b42378@freescale.com>
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Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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---
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arch/arm/mach-imx/clk-imx6q.c | 9 +++++----
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2 files changed, 6 insertions(+), 4 deletions(-)
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--- a/arch/arm/mach-imx/clk-imx6q.c
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+++ b/arch/arm/mach-imx/clk-imx6q.c
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@@ -182,7 +182,7 @@ static const char *periph2_clk2_sels[] =
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static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
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static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
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static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
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-static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
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+static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
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static const char *gpu_axi_sels[] = { "axi", "ahb", };
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static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
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static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
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@@ -196,7 +196,7 @@ static const char *ipu2_di0_sels[] = { "
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static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
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static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
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static const char *pcie_axi_sels[] = { "axi", "ahb", };
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-static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", };
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+static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
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static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
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static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
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@@ -205,7 +205,7 @@ static const char *vdo_axi_sels[] = { "a
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static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
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static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
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"dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
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- "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
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+ "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
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static const char *cko2_sels[] = {
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"mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
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"gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
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@@ -251,7 +251,7 @@ enum mx6q_clks {
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ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
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sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
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usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
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- spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max
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+ spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max
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};
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static struct clk *clk[clk_max];
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@@ -359,6 +359,7 @@ static void __init imx6q_clocks_init(str
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clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2);
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clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
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+ clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
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clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
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clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
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