02629d8f87
Targets were build tested and patches are refreshed. Signed-off-by: Luka Perkov <luka@openwrt.org> SVN-Revision: 42463
86 lines
1.9 KiB
Diff
86 lines
1.9 KiB
Diff
From e93b9480667cbd0e3a4276e8749279693fe239f4 Mon Sep 17 00:00:00 2001
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From: Andy Gross <agross@codeaurora.org>
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Date: Wed, 14 May 2014 22:49:03 -0500
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Subject: [PATCH 136/182] ARM: ipq8064-ap148: Add i2c pinctrl nodes
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Signed-off-by: Andy Gross <agross@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 17 +++++++++++++++++
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 27 +++++++++++++++++++++++++++
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2 files changed, 44 insertions(+)
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--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
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@@ -14,12 +14,29 @@
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};
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soc {
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+ pinmux@800000 {
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+ i2c4_pins: i2c4_pinmux {
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+ pins = "gpio12", "gpio13";
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+ function = "gsbi4";
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+ bias-disable;
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+ };
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+ };
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+
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gsbi@16300000 {
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qcom,mode = <GSBI_PROT_I2C_UART>;
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status = "ok";
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serial@16340000 {
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status = "ok";
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};
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+
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+ i2c4: i2c@16380000 {
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+ status = "ok";
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+
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+ clock-frequency = <200000>;
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+
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+ pinctrl-0 = <&i2c4_pins>;
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+ pinctrl-names = "default";
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+ };
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};
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};
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};
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -137,6 +137,20 @@
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clock-names = "core", "iface";
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status = "disabled";
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};
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+
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+ i2c@124a0000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x124a0000 0x1000>;
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+ interrupts = <0 196 0>;
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+
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+ clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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};
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gsbi4: gsbi@16300000 {
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@@ -158,6 +172,19 @@
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clock-names = "core", "iface";
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status = "disabled";
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};
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+
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+ i2c@16380000 {
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+ compatible = "qcom,i2c-qup-v1.1.1";
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+ reg = <0x16380000 0x1000>;
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+ interrupts = <0 153 0>;
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+
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+ clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
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+ clock-names = "core", "iface";
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+ status = "disabled";
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+
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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};
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qcom,ssbi@500000 {
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