105 lines
3.2 KiB
Diff
105 lines
3.2 KiB
Diff
From bec8339e917651e51592dd57ed005f8ccd9b0e8d Mon Sep 17 00:00:00 2001
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From: Gabor Juhos <juhosg@openwrt.org>
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Date: Thu, 7 Feb 2013 19:29:38 +0000
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Subject: [PATCH] MIPS: pci-ar71xx: move irq base to the controller structure
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commit 326e8d17d73fdf213f6334917ef46b2ba7b1354a upstream.
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Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/4928/
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Signed-off-by: John Crispin <blogic@openwrt.org>
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---
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arch/mips/pci/pci-ar71xx.c | 32 ++++++++++++++++++++++++--------
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1 file changed, 24 insertions(+), 8 deletions(-)
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--- a/arch/mips/pci/pci-ar71xx.c
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+++ b/arch/mips/pci/pci-ar71xx.c
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@@ -52,6 +52,7 @@ struct ar71xx_pci_controller {
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void __iomem *cfg_base;
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spinlock_t lock;
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int irq;
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+ int irq_base;
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struct pci_controller pci_ctrl;
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struct resource io_res;
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struct resource mem_res;
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@@ -238,23 +239,26 @@ static struct pci_ops ar71xx_pci_ops = {
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static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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+ struct ar71xx_pci_controller *apc;
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void __iomem *base = ath79_reset_base;
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u32 pending;
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+ apc = irq_get_handler_data(irq);
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+
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pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
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__raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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if (pending & AR71XX_PCI_INT_DEV0)
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- generic_handle_irq(ATH79_PCI_IRQ(0));
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+ generic_handle_irq(apc->irq_base + 0);
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else if (pending & AR71XX_PCI_INT_DEV1)
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- generic_handle_irq(ATH79_PCI_IRQ(1));
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+ generic_handle_irq(apc->irq_base + 1);
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else if (pending & AR71XX_PCI_INT_DEV2)
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- generic_handle_irq(ATH79_PCI_IRQ(2));
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+ generic_handle_irq(apc->irq_base + 2);
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else if (pending & AR71XX_PCI_INT_CORE)
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- generic_handle_irq(ATH79_PCI_IRQ(4));
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+ generic_handle_irq(apc->irq_base + 4);
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else
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spurious_interrupt();
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@@ -262,10 +266,14 @@ static void ar71xx_pci_irq_handler(unsig
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static void ar71xx_pci_irq_unmask(struct irq_data *d)
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{
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- unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
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+ struct ar71xx_pci_controller *apc;
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+ unsigned int irq;
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void __iomem *base = ath79_reset_base;
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u32 t;
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+ apc = irq_data_get_irq_chip_data(d);
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+ irq = d->irq - apc->irq_base;
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+
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t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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__raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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@@ -275,10 +283,14 @@ static void ar71xx_pci_irq_unmask(struct
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static void ar71xx_pci_irq_mask(struct irq_data *d)
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{
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- unsigned int irq = d->irq - ATH79_PCI_IRQ_BASE;
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+ struct ar71xx_pci_controller *apc;
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+ unsigned int irq;
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void __iomem *base = ath79_reset_base;
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u32 t;
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+ apc = irq_data_get_irq_chip_data(d);
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+ irq = d->irq - apc->irq_base;
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+
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t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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__raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
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@@ -303,11 +315,15 @@ static void ar71xx_pci_irq_init(struct a
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BUILD_BUG_ON(ATH79_PCI_IRQ_COUNT < AR71XX_PCI_IRQ_COUNT);
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- for (i = ATH79_PCI_IRQ_BASE;
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- i < ATH79_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++)
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+ apc->irq_base = ATH79_PCI_IRQ_BASE;
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+ for (i = apc->irq_base;
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+ i < apc->irq_base + AR71XX_PCI_IRQ_COUNT; i++) {
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irq_set_chip_and_handler(i, &ar71xx_pci_irq_chip,
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handle_level_irq);
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+ irq_set_chip_data(i, apc);
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+ }
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+ irq_set_handler_data(apc->irq, apc);
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irq_set_chained_handler(apc->irq, ar71xx_pci_irq_handler);
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}
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