c9e433206f
Patch cherry-picked from the following location: https://www.codeaurora.org/cgit/quic/qsdk/oss/system/openwrt/commit/?h=release/coconut_ioe4531_2.0&id=5c357bf6c763e4140dddcc9a3bc5f005525a9c0e Changelist, - add more register defines - add EHCI support - fix GPIO pin count to 18 - fix chained irq disabled - fix GMAC0/GMAC1 initial - fix WMAC irq number to 47 - merge the changes of dev-eth.c from the patch to file. Signed-off-by: Miaoqing Pan <miaoqing@codeaurora.org> Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net> SVN-Revision: 46207
100 lines
3.1 KiB
Diff
100 lines
3.1 KiB
Diff
--- a/arch/mips/ath79/irq.c
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+++ b/arch/mips/ath79/irq.c
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@@ -26,6 +26,8 @@
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static void (*ath79_ip2_handler)(void);
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static void (*ath79_ip3_handler)(void);
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+static struct irq_chip ip2_chip;
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+static struct irq_chip ip3_chip;
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static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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@@ -149,8 +151,7 @@ static void ar934x_ip2_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
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}
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@@ -182,7 +183,7 @@ static void qca953x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
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}
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@@ -256,15 +257,13 @@ static void qca955x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca955x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip,
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- handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca955x_ip3_irq_dispatch);
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}
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@@ -345,13 +344,13 @@ static void qca956x_irq_init(void)
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for (i = ATH79_IP2_IRQ_BASE;
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i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip2_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(2), qca956x_ip2_irq_dispatch);
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for (i = ATH79_IP3_IRQ_BASE;
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i < ATH79_IP3_IRQ_BASE + ATH79_IP3_IRQ_COUNT; i++)
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- irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
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+ irq_set_chip_and_handler(i, &ip3_chip, handle_level_irq);
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irq_set_chained_handler(ATH79_CPU_IRQ(3), qca956x_ip3_irq_dispatch);
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@@ -466,8 +465,35 @@ static void qca953x_ip3_handler(void)
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do_IRQ(ATH79_CPU_IRQ(3));
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}
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+static void ath79_ip2_disable(struct irq_data *data)
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+{
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+ disable_irq(ATH79_CPU_IRQ(2));
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+}
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+
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+static void ath79_ip2_enable(struct irq_data *data)
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+{
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+ enable_irq(ATH79_CPU_IRQ(2));
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+}
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+
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+static void ath79_ip3_disable(struct irq_data *data)
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+{
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+ disable_irq(ATH79_CPU_IRQ(3));
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+}
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+
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+static void ath79_ip3_enable(struct irq_data *data)
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+{
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+ enable_irq(ATH79_CPU_IRQ(3));
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+}
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+
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void __init arch_init_irq(void)
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{
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+ ip2_chip = dummy_irq_chip;
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+ ip3_chip = dummy_irq_chip;
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+ ip2_chip.irq_disable = ath79_ip2_disable;
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+ ip2_chip.irq_enable = ath79_ip2_enable;
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+ ip3_chip.irq_disable = ath79_ip3_disable;
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+ ip3_chip.irq_enable = ath79_ip3_enable;
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+
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if (soc_is_ar71xx()) {
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ath79_ip2_handler = ar71xx_ip2_handler;
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ath79_ip3_handler = ar71xx_ip3_handler;
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