102cb4742c
Refresh patches on all 4.4 supported platforms. 077-0005-bgmac-stop-clearing-DMA-receive-control-register-rig.patch removed as now upstream. Compile & run tested: ar71xx - Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
80 lines
2.4 KiB
Diff
80 lines
2.4 KiB
Diff
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -475,15 +475,21 @@
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clocks = <&gcc PCIE_A_CLK>,
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<&gcc PCIE_H_CLK>,
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- <&gcc PCIE_PHY_CLK>;
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- clock-names = "core", "iface", "phy";
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+ <&gcc PCIE_PHY_CLK>,
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+ <&gcc PCIE_AUX_CLK>,
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+ <&gcc PCIE_ALT_REF_CLK>;
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+ clock-names = "core", "iface", "phy", "aux", "ref";
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+
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+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
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+ assigned-clock-rates = <100000000>;
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resets = <&gcc PCIE_ACLK_RESET>,
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<&gcc PCIE_HCLK_RESET>,
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<&gcc PCIE_POR_RESET>,
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<&gcc PCIE_PCI_RESET>,
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- <&gcc PCIE_PHY_RESET>;
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- reset-names = "axi", "ahb", "por", "pci", "phy";
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+ <&gcc PCIE_PHY_RESET>,
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+ <&gcc PCIE_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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pinctrl-0 = <&pcie0_pins>;
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pinctrl-names = "default";
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@@ -521,15 +527,21 @@
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clocks = <&gcc PCIE_1_A_CLK>,
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<&gcc PCIE_1_H_CLK>,
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- <&gcc PCIE_1_PHY_CLK>;
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- clock-names = "core", "iface", "phy";
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+ <&gcc PCIE_1_PHY_CLK>,
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+ <&gcc PCIE_1_AUX_CLK>,
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+ <&gcc PCIE_1_ALT_REF_CLK>;
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+ clock-names = "core", "iface", "phy", "aux", "ref";
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+
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+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
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+ assigned-clock-rates = <100000000>;
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resets = <&gcc PCIE_1_ACLK_RESET>,
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<&gcc PCIE_1_HCLK_RESET>,
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<&gcc PCIE_1_POR_RESET>,
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<&gcc PCIE_1_PCI_RESET>,
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- <&gcc PCIE_1_PHY_RESET>;
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- reset-names = "axi", "ahb", "por", "pci", "phy";
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+ <&gcc PCIE_1_PHY_RESET>,
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+ <&gcc PCIE_1_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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pinctrl-0 = <&pcie1_pins>;
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pinctrl-names = "default";
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@@ -567,15 +579,21 @@
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clocks = <&gcc PCIE_2_A_CLK>,
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<&gcc PCIE_2_H_CLK>,
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- <&gcc PCIE_2_PHY_CLK>;
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- clock-names = "core", "iface", "phy";
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+ <&gcc PCIE_2_PHY_CLK>,
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+ <&gcc PCIE_2_AUX_CLK>,
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+ <&gcc PCIE_2_ALT_REF_CLK>;
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+ clock-names = "core", "iface", "phy", "aux", "ref";
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+
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+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
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+ assigned-clock-rates = <100000000>;
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resets = <&gcc PCIE_2_ACLK_RESET>,
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<&gcc PCIE_2_HCLK_RESET>,
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<&gcc PCIE_2_POR_RESET>,
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<&gcc PCIE_2_PCI_RESET>,
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- <&gcc PCIE_2_PHY_RESET>;
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- reset-names = "axi", "ahb", "por", "pci", "phy";
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+ <&gcc PCIE_2_PHY_RESET>,
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+ <&gcc PCIE_2_EXT_RESET>;
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+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
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pinctrl-0 = <&pcie2_pins>;
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pinctrl-names = "default";
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