814 lines
22 KiB
C
814 lines
22 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright © 2003 Atheros Communications, Inc., All Rights Reserved.
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*/
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/*
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* Manage the atheros ethernet PHY.
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*
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* All definitions in this file are operating system independent!
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*/
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#include <config.h>
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#include <linux/types.h>
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#include <common.h>
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#include <miiphy.h>
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//#include "phy.h"
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//#include "ar7100_soc.h"
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#include "athrs26_phy.h"
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#define phy_reg_read(base, addr, reg, datap) \
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miiphy_read("lq_cpe_eth", addr, reg, datap);
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#define phy_reg_write(base, addr, reg, data) \
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miiphy_write("lq_cpe_eth", addr, reg, data);
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/* PHY selections and access functions */
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typedef enum {
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PHY_SRCPORT_INFO,
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PHY_PORTINFO_SIZE,
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} PHY_CAP_TYPE;
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typedef enum {
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PHY_SRCPORT_NONE,
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PHY_SRCPORT_VLANTAG,
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PHY_SRCPORT_TRAILER,
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} PHY_SRCPORT_TYPE;
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#ifdef DEBUG
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#define DRV_DEBUG 1
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#endif
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//#define DRV_DEBUG 1
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#define DRV_DEBUG_PHYERROR 0x00000001
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#define DRV_DEBUG_PHYCHANGE 0x00000002
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#define DRV_DEBUG_PHYSETUP 0x00000004
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#if DRV_DEBUG
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int athrPhyDebug = DRV_DEBUG_PHYERROR|DRV_DEBUG_PHYCHANGE|DRV_DEBUG_PHYSETUP;
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#define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6) \
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{ \
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if (athrPhyDebug & (FLG)) { \
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logMsg(X0, X1, X2, X3, X4, X5, X6); \
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} \
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}
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#define DRV_MSG(x,a,b,c,d,e,f) \
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logMsg(x,a,b,c,d,e,f)
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#define DRV_PRINT(FLG, X) \
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{ \
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if (athrPhyDebug & (FLG)) { \
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printf X; \
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} \
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}
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#else /* !DRV_DEBUG */
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#define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
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#define DRV_MSG(x,a,b,c,d,e,f)
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#define DRV_PRINT(DBG_SW,X)
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#endif
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#define ATHR_LAN_PORT_VLAN 1
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#define ATHR_WAN_PORT_VLAN 2
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#define ENET_UNIT_LAN 0
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#define TRUE 1
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#define FALSE 0
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#define ATHR_PHY0_ADDR 0x0
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#define ATHR_PHY1_ADDR 0x1
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#define ATHR_PHY2_ADDR 0x2
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#define ATHR_PHY3_ADDR 0x3
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#define ATHR_PHY4_ADDR 0x4
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/*
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* Track per-PHY port information.
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*/
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typedef struct {
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BOOL isEnetPort; /* normal enet port */
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BOOL isPhyAlive; /* last known state of link */
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int ethUnit; /* MAC associated with this phy port */
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uint32_t phyBase;
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uint32_t phyAddr; /* PHY registers associated with this phy port */
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uint32_t VLANTableSetting; /* Value to be written to VLAN table */
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} athrPhyInfo_t;
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/*
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* Per-PHY information, indexed by PHY unit number.
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*/
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static athrPhyInfo_t athrPhyInfo[] = {
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{TRUE, /* phy port 0 -- LAN port 0 */
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FALSE,
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ENET_UNIT_LAN,
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0,
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ATHR_PHY0_ADDR,
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ATHR_LAN_PORT_VLAN
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},
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{TRUE, /* phy port 1 -- LAN port 1 */
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FALSE,
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ENET_UNIT_LAN,
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0,
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ATHR_PHY1_ADDR,
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ATHR_LAN_PORT_VLAN
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},
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{TRUE, /* phy port 2 -- LAN port 2 */
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FALSE,
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ENET_UNIT_LAN,
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0,
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ATHR_PHY2_ADDR,
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ATHR_LAN_PORT_VLAN
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},
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{TRUE, /* phy port 3 -- LAN port 3 */
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FALSE,
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ENET_UNIT_LAN,
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0,
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ATHR_PHY3_ADDR,
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ATHR_LAN_PORT_VLAN
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},
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{TRUE, /* phy port 4 -- WAN port or LAN port 4 */
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FALSE,
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1,
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0,
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ATHR_PHY4_ADDR,
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ATHR_LAN_PORT_VLAN /* Send to all ports */
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},
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{FALSE, /* phy port 5 -- CPU port (no RJ45 connector) */
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TRUE,
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ENET_UNIT_LAN,
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0,
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0x00,
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ATHR_LAN_PORT_VLAN /* Send to all ports */
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},
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};
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#ifdef CFG_ATHRHDR_EN
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typedef struct {
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uint8_t data[ATHRHDR_MAX_DATA];
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uint8_t len;
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uint32_t seq;
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} cmd_resp_t;
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typedef struct {
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uint16_t reg_addr;
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uint16_t cmd_len;
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uint8_t *reg_data;
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}cmd_write_t;
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static cmd_write_t cmd_write,cmd_read;
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static cmd_resp_t cmd_resp;
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static struct eth_device *lan_mac;
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//static atomic_t seqcnt = ATOMIC_INIT(0);
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static int seqcnt = 0;
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static int cmd = 1;
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//volatile uchar AthrHdrPkt[60];
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#endif
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#define ATHR_GLOBALREGBASE 0
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//#define ATHR_PHY_MAX (sizeof(athrPhyInfo) / sizeof(athrPhyInfo[0]))
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#define ATHR_PHY_MAX 5
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/* Range of valid PHY IDs is [MIN..MAX] */
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#define ATHR_ID_MIN 0
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#define ATHR_ID_MAX (ATHR_PHY_MAX-1)
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/* Convenience macros to access myPhyInfo */
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#define ATHR_IS_ENET_PORT(phyUnit) (athrPhyInfo[phyUnit].isEnetPort)
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#define ATHR_IS_PHY_ALIVE(phyUnit) (athrPhyInfo[phyUnit].isPhyAlive)
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#define ATHR_ETHUNIT(phyUnit) (athrPhyInfo[phyUnit].ethUnit)
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#define ATHR_PHYBASE(phyUnit) (athrPhyInfo[phyUnit].phyBase)
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#define ATHR_PHYADDR(phyUnit) (athrPhyInfo[phyUnit].phyAddr)
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#define ATHR_VLAN_TABLE_SETTING(phyUnit) (athrPhyInfo[phyUnit].VLANTableSetting)
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#define ATHR_IS_ETHUNIT(phyUnit, ethUnit) \
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(ATHR_IS_ENET_PORT(phyUnit) && \
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ATHR_ETHUNIT(phyUnit) == (ethUnit))
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#define ATHR_IS_WAN_PORT(phyUnit) (!(ATHR_ETHUNIT(phyUnit)==ENET_UNIT_LAN))
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/* Forward references */
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BOOL athrs26_phy_is_link_alive(int phyUnit);
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static uint32_t athrs26_reg_read(uint16_t reg_addr);
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static void athrs26_reg_write(uint16_t reg_addr,
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uint32_t reg_val);
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/******************************************************************************
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*
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* athrs26_phy_is_link_alive - test to see if the specified link is alive
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*
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* RETURNS:
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* TRUE --> link is alive
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* FALSE --> link is down
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*/
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void athrs26_reg_init()
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{
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athrs26_reg_write(0x200, 0x200);
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athrs26_reg_write(0x300, 0x200);
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athrs26_reg_write(0x400, 0x200);
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athrs26_reg_write(0x500, 0x200);
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athrs26_reg_write(0x600, 0x7d);
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#ifdef S26_VER_1_0
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phy_reg_write(0, 0, 29, 41);
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phy_reg_write(0, 0, 30, 0);
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phy_reg_write(0, 1, 29, 41);
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phy_reg_write(0, 1, 30, 0);
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phy_reg_write(0, 2, 29, 41);
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phy_reg_write(0, 2, 30, 0);
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phy_reg_write(0, 3, 29, 41);
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phy_reg_write(0, 3, 30, 0);
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phy_reg_write(0, 4, 29, 41);
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phy_reg_write(0, 4, 30, 0);
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#endif
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athrs26_reg_write(0x38, 0xc000050e);
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#ifdef CFG_ATHRHDR_EN
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athrs26_reg_write(0x104, 0x4804);
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#else
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athrs26_reg_write(0x104, 0x4004);
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#endif
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athrs26_reg_write(0x60, 0xffffffff);
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athrs26_reg_write(0x64, 0xaaaaaaaa);
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athrs26_reg_write(0x68, 0x55555555);
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athrs26_reg_write(0x6c, 0x0);
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athrs26_reg_write(0x70, 0x41af);
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}
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BOOL
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athrs26_phy_is_link_alive(int phyUnit)
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{
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uint16_t phyHwStatus;
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uint32_t phyBase;
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uint32_t phyAddr;
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phyBase = ATHR_PHYBASE(phyUnit);
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phyAddr = ATHR_PHYADDR(phyUnit);
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phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
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if (phyHwStatus & ATHR_STATUS_LINK_PASS)
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return TRUE;
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return FALSE;
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}
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/******************************************************************************
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*
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* athrs26_phy_setup - reset and setup the PHY associated with
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* the specified MAC unit number.
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*
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* Resets the associated PHY port.
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*
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* RETURNS:
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* TRUE --> associated PHY is alive
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* FALSE --> no LINKs on this ethernet unit
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*/
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BOOL
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athrs26_phy_setup(int ethUnit)
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{
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int phyUnit;
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uint16_t phyHwStatus;
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uint16_t timeout;
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int liveLinks = 0;
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uint32_t phyBase = 0;
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BOOL foundPhy = FALSE;
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uint32_t phyAddr = 0;
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uint32_t regVal;
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/* See if there's any configuration data for this enet */
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/* start auto negogiation on each phy */
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for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
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if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
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continue;
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}
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foundPhy = TRUE;
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phyBase = ATHR_PHYBASE(phyUnit);
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phyAddr = ATHR_PHYADDR(phyUnit);
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phy_reg_write(phyBase, phyAddr, ATHR_AUTONEG_ADVERT,
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ATHR_ADVERTISE_ALL);
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/* Reset PHYs*/
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phy_reg_write(phyBase, phyAddr, ATHR_PHY_CONTROL,
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ATHR_CTRL_AUTONEGOTIATION_ENABLE
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| ATHR_CTRL_SOFTWARE_RESET);
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}
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if (!foundPhy) {
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return FALSE; /* No PHY's configured for this ethUnit */
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}
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/*
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* After the phy is reset, it takes a little while before
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* it can respond properly.
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*/
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sysMsDelay(1000);
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/*
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* Wait up to .75 seconds for ALL associated PHYs to finish
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* autonegotiation. The only way we get out of here sooner is
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* if ALL PHYs are connected AND finish autonegotiation.
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*/
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for (phyUnit=0; (phyUnit < ATHR_PHY_MAX) /*&& (timeout > 0) */; phyUnit++) {
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if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
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continue;
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}
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timeout=20;
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for (;;) {
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phyHwStatus = 0;
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phy_reg_read(phyBase, phyAddr, ATHR_PHY_CONTROL, &phyHwStatus);
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if (ATHR_RESET_DONE(phyHwStatus)) {
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DRV_PRINT(DRV_DEBUG_PHYSETUP,
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("Port %d, Neg Success\n", phyUnit));
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break;
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}
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if (timeout == 0) {
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DRV_PRINT(DRV_DEBUG_PHYSETUP,
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("Port %d, Negogiation timeout\n", phyUnit));
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break;
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}
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if (--timeout == 0) {
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DRV_PRINT(DRV_DEBUG_PHYSETUP,
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("Port %d, Negogiation timeout\n", phyUnit));
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break;
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}
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sysMsDelay(150);
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}
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}
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/*
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* All PHYs have had adequate time to autonegotiate.
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* Now initialize software status.
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*
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* It's possible that some ports may take a bit longer
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* to autonegotiate; but we can't wait forever. They'll
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* get noticed by mv_phyCheckStatusChange during regular
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* polling activities.
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*/
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for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
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if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
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continue;
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}
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if (athrs26_phy_is_link_alive(phyUnit)) {
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liveLinks++;
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ATHR_IS_PHY_ALIVE(phyUnit) = TRUE;
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} else {
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ATHR_IS_PHY_ALIVE(phyUnit) = FALSE;
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}
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phy_reg_read(ATHR_PHYBASE(phyUnit), ATHR_PHYADDR(phyUnit),
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ATHR_PHY_SPEC_STATUS, ®Val);
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DRV_PRINT(DRV_DEBUG_PHYSETUP,
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("eth%d: Phy Specific Status=%4.4x\n", ethUnit, regVal));
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}
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#if 0
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/* if using header for register configuration, we have to */
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/* configure s26 register after frame transmission is enabled */
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athrs26_reg_write(0x200, 0x200);
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athrs26_reg_write(0x300, 0x200);
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athrs26_reg_write(0x400, 0x200);
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athrs26_reg_write(0x500, 0x200);
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athrs26_reg_write(0x600, 0x200);
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athrs26_reg_write(0x38, 0x50e);
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#endif
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#ifndef CFG_ATHRHDR_EN
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/* if using header for register configuration, we have to */
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/* configure s26 register after frame transmission is enabled */
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athrs26_reg_init();
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#endif
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return (liveLinks > 0);
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}
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/******************************************************************************
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*
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* athrs26_phy_is_fdx - Determines whether the phy ports associated with the
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* specified device are FULL or HALF duplex.
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*
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* RETURNS:
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* 1 --> FULL
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* 0 --> HALF
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*/
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int
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athrs26_phy_is_fdx(int ethUnit)
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{
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int phyUnit;
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uint32_t phyBase;
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uint32_t phyAddr;
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uint16_t phyHwStatus;
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int ii = 200;
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if (ethUnit == ENET_UNIT_LAN)
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return TRUE;
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for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
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if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
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continue;
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}
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if (athrs26_phy_is_link_alive(phyUnit)) {
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phyBase = ATHR_PHYBASE(phyUnit);
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phyAddr = ATHR_PHYADDR(phyUnit);
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do {
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phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
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sysMsDelay(10);
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} while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
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if (phyHwStatus & ATHER_STATUS_FULL_DEPLEX)
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return TRUE;
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}
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}
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return FALSE;
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}
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/******************************************************************************
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*
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* athrs26_phy_speed - Determines the speed of phy ports associated with the
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* specified device.
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*
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* RETURNS:
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* AG7100_PHY_SPEED_10T, AG7100_PHY_SPEED_100TX;
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* AG7100_PHY_SPEED_1000T;
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*/
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BOOL
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athrs26_phy_speed(int ethUnit)
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{
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int phyUnit;
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uint16_t phyHwStatus;
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uint32_t phyBase;
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uint32_t phyAddr;
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int ii = 200;
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if (ethUnit == ENET_UNIT_LAN)
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return _100BASET;
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for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
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if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
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continue;
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}
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if (athrs26_phy_is_link_alive(phyUnit)) {
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phyBase = ATHR_PHYBASE(phyUnit);
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phyAddr = ATHR_PHYADDR(phyUnit);
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do {
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phy_reg_read(phyBase, phyAddr,
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ATHR_PHY_SPEC_STATUS, &phyHwStatus);
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sysMsDelay(10);
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}while((!(phyHwStatus & ATHR_STATUS_RESOVLED)) && --ii);
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phyHwStatus = ((phyHwStatus & ATHER_STATUS_LINK_MASK) >>
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ATHER_STATUS_LINK_SHIFT);
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switch(phyHwStatus) {
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case 0:
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return _10BASET;
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case 1:
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return _100BASET;
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case 2:
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return _1000BASET;
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default:
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DRV_PRINT(DRV_DEBUG_PHYERROR, ("Unkown speed read!\n"));
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}
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}
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}
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return _10BASET;
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}
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/*****************************************************************************
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*
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* athr_phy_is_up -- checks for significant changes in PHY state.
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*
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* A "significant change" is:
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* dropped link (e.g. ethernet cable unplugged) OR
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* autonegotiation completed + link (e.g. ethernet cable plugged in)
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*
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* When a PHY is plugged in, phyLinkGained is called.
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* When a PHY is unplugged, phyLinkLost is called.
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*/
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int
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athrs26_phy_is_up(int ethUnit)
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|
{
|
|
int phyUnit;
|
|
uint16_t phyHwStatus;
|
|
athrPhyInfo_t *lastStatus;
|
|
int linkCount = 0;
|
|
int lostLinks = 0;
|
|
int gainedLinks = 0;
|
|
uint32_t phyBase;
|
|
uint32_t phyAddr;
|
|
#ifdef CFG_ATHRHDR_REG
|
|
/* if using header to config s26, the link of MAC0 should always be up */
|
|
if (ethUnit == ENET_UNIT_LAN)
|
|
return 1;
|
|
#endif
|
|
|
|
for (phyUnit=0; phyUnit < ATHR_PHY_MAX; phyUnit++) {
|
|
if (!ATHR_IS_ETHUNIT(phyUnit, ethUnit)) {
|
|
continue;
|
|
}
|
|
|
|
phyBase = ATHR_PHYBASE(phyUnit);
|
|
phyAddr = ATHR_PHYADDR(phyUnit);
|
|
|
|
|
|
lastStatus = &athrPhyInfo[phyUnit];
|
|
phy_reg_read(phyBase, phyAddr, ATHR_PHY_SPEC_STATUS, &phyHwStatus);
|
|
|
|
if (lastStatus->isPhyAlive) { /* last known link status was ALIVE */
|
|
/* See if we've lost link */
|
|
if (phyHwStatus & ATHR_STATUS_LINK_PASS) {
|
|
linkCount++;
|
|
} else {
|
|
lostLinks++;
|
|
DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d down\n",
|
|
ethUnit, phyUnit));
|
|
lastStatus->isPhyAlive = FALSE;
|
|
}
|
|
} else { /* last known link status was DEAD */
|
|
/* Check for reset complete */
|
|
phy_reg_read(phyBase, phyAddr, ATHR_PHY_STATUS, &phyHwStatus);
|
|
if (!ATHR_RESET_DONE(phyHwStatus))
|
|
continue;
|
|
|
|
/* Check for AutoNegotiation complete */
|
|
if (ATHR_AUTONEG_DONE(phyHwStatus)) {
|
|
//printk("autoneg done\n");
|
|
gainedLinks++;
|
|
linkCount++;
|
|
DRV_PRINT(DRV_DEBUG_PHYCHANGE,("\nenet%d port%d up\n",
|
|
ethUnit, phyUnit));
|
|
lastStatus->isPhyAlive = TRUE;
|
|
}
|
|
}
|
|
}
|
|
|
|
return (linkCount);
|
|
|
|
#if 0
|
|
if (linkCount == 0) {
|
|
if (lostLinks) {
|
|
/* We just lost the last link for this MAC */
|
|
phyLinkLost(ethUnit);
|
|
}
|
|
} else {
|
|
if (gainedLinks == linkCount) {
|
|
/* We just gained our first link(s) for this MAC */
|
|
phyLinkGained(ethUnit);
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
#ifdef CFG_ATHRHDR_EN
|
|
void athr_hdr_timeout(void){
|
|
eth_halt();
|
|
NetState = NETLOOP_FAIL;
|
|
}
|
|
|
|
void athr_hdr_handler(uchar *recv_pkt, unsigned dest, unsigned src, unsigned len){
|
|
header_receive_pkt(recv_pkt);
|
|
NetState = NETLOOP_SUCCESS;
|
|
}
|
|
static int
|
|
athrs26_header_config_reg (struct eth_device *dev, uint8_t wr_flag,
|
|
uint16_t reg_addr, uint16_t cmd_len,
|
|
uint8_t *val)
|
|
{
|
|
at_header_t at_header;
|
|
reg_cmd_t reg_cmd;
|
|
uchar *AthrHdrPkt;
|
|
|
|
AthrHdrPkt = NetTxPacket;
|
|
|
|
if(AthrHdrPkt == NULL) {
|
|
printf("Null packet\n");
|
|
return;
|
|
}
|
|
memset(AthrHdrPkt,0,60);
|
|
|
|
/*fill at_header*/
|
|
at_header.reserved0 = 0x10; //default
|
|
at_header.priority = 0;
|
|
at_header.type = 0x5;
|
|
at_header.broadcast = 0;
|
|
at_header.from_cpu = 1;
|
|
at_header.reserved1 = 0x01; //default
|
|
at_header.port_num = 0;
|
|
|
|
AthrHdrPkt[0] = at_header.port_num;
|
|
AthrHdrPkt[0] |= at_header.reserved1 << 4;
|
|
AthrHdrPkt[0] |= at_header.from_cpu << 6;
|
|
AthrHdrPkt[0] |= at_header.broadcast << 7;
|
|
|
|
AthrHdrPkt[1] = at_header.type;
|
|
AthrHdrPkt[1] |= at_header.priority << 4;
|
|
AthrHdrPkt[1] |= at_header.reserved0 << 6;
|
|
|
|
|
|
/*fill reg cmd*/
|
|
if(cmd_len > 4)
|
|
cmd_len = 4;//only support 32bits register r/w
|
|
|
|
reg_cmd.reg_addr = reg_addr&0x3FFFC;
|
|
reg_cmd.cmd_len = cmd_len;
|
|
reg_cmd.cmd = wr_flag;
|
|
reg_cmd.reserved2 = 0x5; //default
|
|
reg_cmd.seq_num = seqcnt;
|
|
|
|
AthrHdrPkt[2] = reg_cmd.reg_addr & 0xff;
|
|
AthrHdrPkt[3] = (reg_cmd.reg_addr & 0xff00) >> 8;
|
|
AthrHdrPkt[4] = (reg_cmd.reg_addr & 0x30000) >> 16;
|
|
AthrHdrPkt[4] |= reg_cmd.cmd_len << 4;
|
|
AthrHdrPkt[5] = reg_cmd.cmd << 4;
|
|
AthrHdrPkt[5] |= reg_cmd.reserved2 << 5;
|
|
AthrHdrPkt[6] = (reg_cmd.seq_num & 0x7f) << 1;
|
|
AthrHdrPkt[7] = (reg_cmd.seq_num & 0x7f80) >> 7;
|
|
AthrHdrPkt[8] = (reg_cmd.seq_num & 0x7f8000) >> 15;
|
|
AthrHdrPkt[9] = (reg_cmd.seq_num & 0x7f800000) >> 23;
|
|
|
|
/*fill reg data*/
|
|
if(!wr_flag)//write
|
|
memcpy((AthrHdrPkt + 10), val, cmd_len);
|
|
|
|
/*start xmit*/
|
|
if(dev == NULL) {
|
|
printf("ERROR device not found\n");
|
|
return -1;
|
|
}
|
|
header_xmit(dev, AthrHdrPkt ,60);
|
|
return 0;
|
|
}
|
|
void athr_hdr_func(void) {
|
|
|
|
NetSetTimeout (1 * CFG_HZ,athr_hdr_timeout );
|
|
NetSetHandler (athr_hdr_handler);
|
|
|
|
if(cmd)
|
|
athrs26_header_config_reg(lan_mac, cmd, cmd_read.reg_addr, cmd_read.cmd_len, cmd_read.reg_data);
|
|
else
|
|
athrs26_header_config_reg(lan_mac, cmd, cmd_write.reg_addr, cmd_write.cmd_len, cmd_write.reg_data);
|
|
}
|
|
static int
|
|
athrs26_header_write_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
|
|
{
|
|
int i = 2;
|
|
cmd_write.reg_addr = reg_addr;
|
|
cmd_write.cmd_len = cmd_len;
|
|
cmd_write.reg_data = reg_data;
|
|
cmd = 0;
|
|
seqcnt++;
|
|
|
|
do {
|
|
if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
|
|
break;
|
|
} while (i--);
|
|
|
|
return i;
|
|
}
|
|
|
|
static int
|
|
athrs26_header_read_reg(uint16_t reg_addr, uint16_t cmd_len, uint8_t *reg_data)
|
|
{
|
|
int i = 2;
|
|
|
|
cmd_read.reg_addr = reg_addr;
|
|
cmd_read.cmd_len = cmd_len;
|
|
cmd_read.reg_data = reg_data;
|
|
cmd = 1;
|
|
seqcnt++;
|
|
|
|
do {
|
|
if (NetLoop(ATHRHDR) >= 0) /* polls for read/write ack from PHY */
|
|
break;
|
|
} while (i--);
|
|
|
|
if ((i==0) || (seqcnt != cmd_resp.seq) || (cmd_len != cmd_resp.len)) {
|
|
return -1;
|
|
}
|
|
memcpy (cmd_read.reg_data, cmd_resp.data, cmd_len);
|
|
return 0;
|
|
}
|
|
int header_receive_pkt(uchar *recv_pkt)
|
|
{
|
|
cmd_resp.len = recv_pkt[4] >> 4;
|
|
if (cmd_resp.len > 10)
|
|
goto out;
|
|
|
|
cmd_resp.seq = recv_pkt[6] >> 1;
|
|
cmd_resp.seq |= recv_pkt[7] << 7;
|
|
cmd_resp.seq |= recv_pkt[8] << 15;
|
|
cmd_resp.seq |= recv_pkt[9] << 23;
|
|
|
|
if (cmd_resp.seq < seqcnt)
|
|
goto out;
|
|
memcpy (cmd_resp.data, (recv_pkt + 10), cmd_resp.len);
|
|
out:
|
|
return 0;
|
|
}
|
|
|
|
void athrs26_reg_dev(struct eth_device *mac)
|
|
{
|
|
lan_mac = mac;
|
|
}
|
|
|
|
#endif
|
|
|
|
static uint32_t
|
|
athrs26_reg_read(uint16_t reg_addr)
|
|
{
|
|
#ifndef CFG_ATHRHDR_REG
|
|
uint16_t reg_word_addr = reg_addr / 2, phy_val;
|
|
uint32_t phy_addr;
|
|
uint8_t phy_reg;
|
|
|
|
/* configure register high address */
|
|
phy_addr = 0x18;
|
|
phy_reg = 0x0;
|
|
phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
|
|
phy_reg_write (0, phy_addr, phy_reg, phy_val);
|
|
|
|
/* read register with low address */
|
|
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
|
phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address*/
|
|
phy_reg_read(0, phy_addr, phy_reg, &phy_val);
|
|
|
|
return phy_val;
|
|
#else
|
|
uint8_t reg_data[4];
|
|
|
|
memset (reg_data, 0, 4);
|
|
athrs26_header_read_reg(reg_addr, 4, reg_data);
|
|
return (reg_data[0] | (reg_data[1] << 8) | (reg_data[2] << 16) | (reg_data[3] << 24));
|
|
#endif
|
|
}
|
|
|
|
static void
|
|
athrs26_reg_write(uint16_t reg_addr, uint32_t reg_val)
|
|
{
|
|
#ifndef CFG_ATHRHDR_REG
|
|
uint16_t reg_word_addr = reg_addr / 2, phy_val;
|
|
uint32_t phy_addr;
|
|
uint8_t phy_reg;
|
|
|
|
/* configure register high address */
|
|
phy_addr = 0x18;
|
|
phy_reg = 0x0;
|
|
phy_val = (reg_word_addr >> 8) & 0x1ff; /* bit16-8 of reg address*/
|
|
phy_reg_write (0, phy_addr, phy_reg, phy_val);
|
|
|
|
/* read register with low address */
|
|
phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
|
|
phy_reg = reg_word_addr & 0x1f; /* bit 4-0 of reg address */
|
|
phy_reg_write (0, phy_addr, phy_reg, reg_val);
|
|
#else
|
|
uint8_t reg_data[4];
|
|
|
|
memset (reg_data, 0, 4);
|
|
reg_data[0] = (uint8_t)(0x00ff & reg_val);
|
|
reg_data[1] = (uint8_t)((0xff00 & reg_val) >> 8);
|
|
reg_data[2] = (uint8_t)((0xff0000 & reg_val) >> 16);
|
|
reg_data[3] = (uint8_t)((0xff000000 & reg_val) >> 24);
|
|
|
|
athrs26_header_write_reg (reg_addr, 4, reg_data);
|
|
#endif
|
|
|
|
}
|
|
|