72b58f2eb1
This is the oxnas target previously developed at http://gitorious.org/openwrt-oxnas Basically, this consolidates the changes and addtionas from http://github.org/kref/linux-oxnas into a new OpenWrt hardware target 'oxnas' adding support for PLX Technology NAS7820/NAS7821/NAS7825/... formally known as Oxford Semiconductor OXE810SE/OXE815/OX820/... For now there are 4 supported boards: Cloud Engines Pogoplug V3 (without PCIe) fully supported Cloud Engines Pogoplug Pro (with PCIe) fully supported MitraStar STG-212 aka ZyXEL NSA-212, aka Medion Akoya P89625 / P89636 / P89626 / P89630, aka Medion MD 86407 / MD 86805 / MD 86517 / MD 86587 fully supported, see http://wiki.openwrt.org/toh/medion/md86587 Shuttle KD-20 partially supported (S-ATA driver lacks support for 2nd port) Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43388
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
/*
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* arch/arm/mach-ox820/rps-time.c
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*
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* Copyright (C) 2009 Oxford Semiconductor Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/clockchips.h>
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#include <linux/clk.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/sched_clock.h>
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#include <mach/hardware.h>
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enum {
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TIMER_LOAD = 0,
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TIMER_CURR = 4,
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TIMER_CTRL = 8,
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TIMER_CLRINT = 0xC,
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TIMER_BITS = 24,
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TIMER_MAX_VAL = (1 << TIMER_BITS) - 1,
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TIMER_PERIODIC = (1 << 6),
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TIMER_ENABLE = (1 << 7),
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TIMER_DIV1 = (0 << 2),
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TIMER_DIV16 = (1 << 2),
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TIMER_DIV256 = (2 << 2),
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TIMER1_OFFSET = 0,
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TIMER2_OFFSET = 0x20,
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};
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static u64 notrace rps_read_sched_clock(void)
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{
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return ~readl_relaxed(RPSA_TIMER2_VAL);
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}
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static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate)
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{
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int ret;
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ulong clock_rate;
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/* use prescale 16 */
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clock_rate = ref_rate / 16;
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iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD);
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iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16,
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base + TIMER_CTRL);
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ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer",
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clock_rate, 250, TIMER_BITS,
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clocksource_mmio_readl_down);
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if (ret)
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panic("can't register clocksource\n");
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sched_clock_register(rps_read_sched_clock, TIMER_BITS, clock_rate);
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}
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static void __init rps_timer_init(struct device_node *np)
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{
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struct clk *refclk;
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unsigned long ref_rate;
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void __iomem *base;
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refclk = of_clk_get(np, 0);
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if (IS_ERR(refclk) || clk_prepare_enable(refclk))
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panic("rps_timer_init: failed to get refclk\n");
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ref_rate = clk_get_rate(refclk);
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base = of_iomap(np, 0);
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if (!base)
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panic("rps_timer_init: failed to map io\n");
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rps_clocksource_init(base + TIMER2_OFFSET, ref_rate);
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}
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CLOCKSOURCE_OF_DECLARE(nas782x, "plxtech,nas782x-rps-timer", rps_timer_init);
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