c05048b0bb
This adds support for the oxnas target in U-Boot 2014.04 History can be found at https://github.com/kref/u-boot-oxnas up to 2013.10 changes from 2013.10 to 2014.04 can be followed at https://gitorious.org/openwrt-oxnas Signed-off-by: Daniel Golle <daniel@makrotopia.org> SVN-Revision: 43389
105 lines
3 KiB
C
105 lines
3 KiB
C
/*
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* drivers/usb/host/ehci-oxnas.c
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*
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* Tzachi Perelstein <tzachi@marvell.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sysctl.h>
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#include <asm/arch/clock.h>
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#include "ehci.h"
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static struct ehci_hcor *ghcor;
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static int start_oxnas_usb_ehci(void)
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{
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#ifdef CONFIG_USB_PLLB_CLK
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reset_block(SYS_CTRL_RST_PLLB, 0);
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enable_clock(SYS_CTRL_CLK_REF600);
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writel((1 << PLLB_ENSAT) | (1 << PLLB_OUTDIV) | (2 << PLLB_REFDIV),
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SEC_CTRL_PLLB_CTRL0);
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/* 600MHz pllb divider for 12MHz */
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writel(PLLB_DIV_INT(50) | PLLB_DIV_FRAC(0), SEC_CTRL_PLLB_DIV_CTRL);
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#else
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/* ref 300 divider for 12MHz */
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writel(REF300_DIV_INT(25) | REF300_DIV_FRAC(0), SYS_CTRL_REF300_DIV);
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#endif
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/* Ensure the USB block is properly reset */
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reset_block(SYS_CTRL_RST_USBHS, 1);
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reset_block(SYS_CTRL_RST_USBHS, 0);
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reset_block(SYS_CTRL_RST_USBHSPHYA, 1);
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reset_block(SYS_CTRL_RST_USBHSPHYA, 0);
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reset_block(SYS_CTRL_RST_USBHSPHYB, 1);
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reset_block(SYS_CTRL_RST_USBHSPHYB, 0);
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/* Force the high speed clock to be generated all the time, via serial
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programming of the USB HS PHY */
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writel((2UL << USBHSPHY_TEST_ADD) |
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(0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
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writel((1UL << USBHSPHY_TEST_CLK) |
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(2UL << USBHSPHY_TEST_ADD) |
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(0xe0UL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
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writel((0xfUL << USBHSPHY_TEST_ADD) |
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(0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
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writel((1UL << USBHSPHY_TEST_CLK) |
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(0xfUL << USBHSPHY_TEST_ADD) |
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(0xaaUL << USBHSPHY_TEST_DIN), SYS_CTRL_USBHSPHY_CTRL);
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#ifdef CONFIG_USB_PLLB_CLK /* use pllb clock */
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writel(USB_CLK_INTERNAL | USB_INT_CLK_PLLB, SYS_CTRL_USB_CTRL);
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#else /* use ref300 derived clock */
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writel(USB_CLK_INTERNAL | USB_INT_CLK_REF300, SYS_CTRL_USB_CTRL);
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#endif
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/* Enable the clock to the USB block */
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enable_clock(SYS_CTRL_CLK_USBHS);
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
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struct ehci_hcor **hcor)
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{
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start_oxnas_usb_ehci();
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*hccr = (struct ehci_hccr *)(USB_HOST_BASE + 0x100);
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*hcor = (struct ehci_hcor *)((uint32_t)*hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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ghcor = *hcor;
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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reset_block(SYS_CTRL_RST_USBHS, 1);
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disable_clock(SYS_CTRL_CLK_USBHS);
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return 0;
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}
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extern void __ehci_set_usbmode(int index);
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void ehci_set_usbmode(int index)
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{
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#define or_txttfill_tuning _reserved_1_[0]
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u32 tmp;
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__ehci_set_usbmode(index);
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tmp = ehci_readl(&ghcor->or_txfilltuning);
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tmp &= ~0x00ff0000;
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tmp |= 0x003f0000; /* set burst pre load count to 0x40 (63 * 4 bytes) */
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tmp |= 0x16; /* set sheduler overhead to 22 * 1.267us (HS) or 22 * 6.33us (FS/LS)*/
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ehci_writel(&ghcor->or_txfilltuning, tmp);
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tmp = ehci_readl(&ghcor->or_txttfill_tuning);
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tmp |= 0x2; /* set sheduler overhead to 2 * 6.333us */
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ehci_writel(&ghcor->or_txttfill_tuning, tmp);
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}
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