ec1de9b1a6
The Dlink DWR-512-B modem is a ralink 5350 processor based embedding a 3G mini-pcie router. The oem JBOOT bootloader has to be replaced by a RT5350 SDK U-Boot such as https://github.com/stevenylai/ralink_sdk - U-Boot configured for the RT5350 256MiB SDR. Main reason to change the bootloader is the encrypted header used to store the kernel image. In this way an image can only be generated using the propietary binboy tool (included in the GPL distribution from Dlink). The binboy tool doesn't allow to modify the kernel/rootfs partition scheme. This is considered a big constraint (limited kernel size and inefficient usage of flash space). For interested people I pubblished the details of my investigation about the encrypted firmware header here: http://lists.infradead.org/pipermail/lede-dev/2016-October/003435.html Signed-off-by: Giuseppe Lippolis <giu.lippolis@gmail.com>
128 lines
2.1 KiB
Text
128 lines
2.1 KiB
Text
/dts-v1/;
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#include "rt5350.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "ralink,rt5350-soc";
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model = "D-Link DWR-512 B";
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gpio-keys-polled {
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compatible = "gpio-keys-polled";
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#address-cells = <1>;
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#size-cells = <0>;
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poll-interval = <20>;
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wps {
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label = "wps";
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gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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reset {
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label = "reset";
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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sms {
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label = "dwr-512-b:green:sms";
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gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
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};
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status {
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label = "dwr-512-b:green:status";
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gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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};
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2g {
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label = "dwr-512-b:green:2g";
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gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
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};
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3g {
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label = "dwr-512-b:green:3g";
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gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
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};
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sstrengthr {
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label = "dwr-512-b:red:sigstrength";
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gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
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};
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sstrengthg {
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label = "dwr-512-b:green:sigstrength";
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gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-export {
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compatible = "gpio-export";
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#size-cells = <0>;
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modem3g_enable {
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gpio-export,name = "modem3g_enable";
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gpio-export,output = <1>;
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gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&spi0 {
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status = "okay";
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mx25l6405d@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <30000000>;
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m25p,fast-read;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x20000>;
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read-only;
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};
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partition@50000 {
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label = "firmware";
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reg = <0x50000 0x7a0000>;
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};
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config: partition@7f0000 {
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label = "config";
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reg = <0x7f0000 0x10000>;
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};
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};
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};
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&pinctrl {
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state_default: pinctrl0 {
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gpio {
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ralink,group = "i2c", "jtag", "uartf";
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ralink,function = "gpio";
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};
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};
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};
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&esw {
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mediatek,portmap = <0x2f>;
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};
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ðernet {
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mtd-mac-address = <&config 0xe07e>;
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};
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&wmac {
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ralink,mtd-eeprom = <&config 0xe08a>;
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ralink,led-polarity = <1>;
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mtd-mac-address = <&config 0xe07e>;
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};
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