4fd9028f44
These patches are written by Broadcom and will be in mainline Linux kernel soon. I had some problems to get them backported to kernel 4.1, so currently they are only available for 4.3. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> SVN-Revision: 47253
59 lines
2 KiB
Diff
59 lines
2 KiB
Diff
From 63243a4da7d0dfa19dcacd0a529782eeb2f86f92 Mon Sep 17 00:00:00 2001
|
|
From: Simran Rai <ssimran@broadcom.com>
|
|
Date: Mon, 19 Oct 2015 15:27:19 -0700
|
|
Subject: [PATCH] clk: iproc: Fix PLL output frequency calculation
|
|
|
|
This patch affects the clocks that use fractional ndivider in their
|
|
PLL output frequency calculation. Instead of 2^20 divide factor, the
|
|
clock's ndiv integer shift was used. Fixed the bug by replacing ndiv
|
|
integer shift with 2^20 factor.
|
|
|
|
Signed-off-by: Simran Rai <ssimran@broadcom.com>
|
|
Signed-off-by: Ray Jui <rjui@broadcom.com>
|
|
Reviewed-by: Scott Branden <sbranden@broadcom.com>
|
|
Fixes: 5fe225c105fd ("clk: iproc: add initial common clock support")
|
|
Cc: <stable@vger.kernel.org> # v4.1+
|
|
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
|
|
---
|
|
drivers/clk/bcm/clk-iproc-pll.c | 13 +++++--------
|
|
1 file changed, 5 insertions(+), 8 deletions(-)
|
|
|
|
--- a/drivers/clk/bcm/clk-iproc-pll.c
|
|
+++ b/drivers/clk/bcm/clk-iproc-pll.c
|
|
@@ -345,8 +345,8 @@ static unsigned long iproc_pll_recalc_ra
|
|
struct iproc_pll *pll = clk->pll;
|
|
const struct iproc_pll_ctrl *ctrl = pll->ctrl;
|
|
u32 val;
|
|
- u64 ndiv;
|
|
- unsigned int ndiv_int, ndiv_frac, pdiv;
|
|
+ u64 ndiv, ndiv_int, ndiv_frac;
|
|
+ unsigned int pdiv;
|
|
|
|
if (parent_rate == 0)
|
|
return 0;
|
|
@@ -366,22 +366,19 @@ static unsigned long iproc_pll_recalc_ra
|
|
val = readl(pll->pll_base + ctrl->ndiv_int.offset);
|
|
ndiv_int = (val >> ctrl->ndiv_int.shift) &
|
|
bit_mask(ctrl->ndiv_int.width);
|
|
- ndiv = (u64)ndiv_int << ctrl->ndiv_int.shift;
|
|
+ ndiv = ndiv_int << 20;
|
|
|
|
if (ctrl->flags & IPROC_CLK_PLL_HAS_NDIV_FRAC) {
|
|
val = readl(pll->pll_base + ctrl->ndiv_frac.offset);
|
|
ndiv_frac = (val >> ctrl->ndiv_frac.shift) &
|
|
bit_mask(ctrl->ndiv_frac.width);
|
|
-
|
|
- if (ndiv_frac != 0)
|
|
- ndiv = ((u64)ndiv_int << ctrl->ndiv_int.shift) |
|
|
- ndiv_frac;
|
|
+ ndiv += ndiv_frac;
|
|
}
|
|
|
|
val = readl(pll->pll_base + ctrl->pdiv.offset);
|
|
pdiv = (val >> ctrl->pdiv.shift) & bit_mask(ctrl->pdiv.width);
|
|
|
|
- clk->rate = (ndiv * parent_rate) >> ctrl->ndiv_int.shift;
|
|
+ clk->rate = (ndiv * parent_rate) >> 20;
|
|
|
|
if (pdiv == 0)
|
|
clk->rate *= 2;
|