358 lines
12 KiB
C
358 lines
12 KiB
C
/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2005 infineon
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*
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*/
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#ifndef _DANUBE_H__
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#define _DANUBE_H__
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/*------------ GENERAL */
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#define BOARD_SYSTEM_TYPE "DANUBE"
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#define IOPORT_RESOURCE_START 0x10000000
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#define IOPORT_RESOURCE_END 0xffffffff
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#define IOMEM_RESOURCE_START 0x10000000
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#define IOMEM_RESOURCE_END 0xffffffff
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/*------------ ASC1 */
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#define DANUBE_ASC1_BASE_ADDR (KSEG1 + 0x1E100C00)
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/* FIFO status register */
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#define DANUBE_ASC1_FSTAT ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0048))
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFFLOFF 8
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/* ASC1 transmit buffer */
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#define DANUBE_ASC1_TBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0020))
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/* channel operating modes */
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#define ASCOPT_CSIZE 0x3
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#define ASCOPT_CS7 0x1
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#define ASCOPT_CS8 0x2
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#define ASCOPT_PARENB 0x4
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#define ASCOPT_STOPB 0x8
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#define ASCOPT_PARODD 0x0
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#define ASCOPT_CREAD 0x20
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/* hardware modified control register */
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#define DANUBE_ASC1_WHBSTATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0018))
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/* receive buffer register */
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#define DANUBE_ASC1_RBUF ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0024))
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/* status register */
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#define DANUBE_ASC1_STATE ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0014))
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/* interrupt control */
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#define DANUBE_ASC1_IRNCR ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F8))
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#define ASC_IRNCR_TIR 0x4
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#define ASC_IRNCR_RIR 0x2
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#define ASC_IRNCR_EIR 0x4
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/* clock control */
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#define DANUBE_ASC1_CLC ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0000))
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#define DANUBE_ASC1_CLC_DISS 0x2
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/* port input select register */
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#define DANUBE_ASC1_PISEL ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0004))
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/* tx fifo */
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#define DANUBE_ASC1_TXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0044))
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/* rx fifo */
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#define DANUBE_ASC1_RXFCON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0040))
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/* control */
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#define DANUBE_ASC1_CON ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0010))
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/* timer reload */
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#define DANUBE_ASC1_BG ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x0050))
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/* int enable */
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#define DANUBE_ASC1_IRNREN ((u32*)(DANUBE_ASC1_BASE_ADDR + 0x00F4))
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#define ASC_IRNREN_RX_BUF 0x8
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#define ASC_IRNREN_TX_BUF 0x4
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#define ASC_IRNREN_ERR 0x2
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#define ASC_IRNREN_TX 0x1
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/*------------ RCU */
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#define DANUBE_RCU_BASE_ADDR 0xBF203000
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/* reset request */
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#define DANUBE_RCU_REQ ((u32*)(DANUBE_RCU_BASE_ADDR + 0x0010))
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#define DANUBE_RST_ALL 0x40000000
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/*------------ MCD */
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#define DANUBE_MCD_BASE_ADDR (KSEG1 + 0x1F106000)
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/* chip id */
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#define DANUBE_MCD_CHIPID ((u32*)(DANUBE_MCD_BASE_ADDR + 0x0028))
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/*------------ GPTU */
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#define DANUBE_GPTU_BASE_ADDR 0xB8000300
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/* clock control register */
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#define DANUBE_GPTU_GPT_CLC ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0000))
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/* captur reload register */
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#define DANUBE_GPTU_GPT_CAPREL ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0030))
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/* timer 6 control register */
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#define DANUBE_GPTU_GPT_T6CON ((u32*)(DANUBE_GPTU_BASE_ADDR + 0x0020))
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/*------------ EBU */
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#define DANUBE_EBU_BASE_ADDR 0xBE105300
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/* bus configuration register */
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#define DANUBE_EBU_BUSCON0 ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0060))
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#define DANUBE_EBU_PCC_CON ((u32*)(DANUBE_EBU_BASE_ADDR + 0x0090))
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#define DANUBE_EBU_PCC_IEN ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A4))
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#define DANUBE_EBU_PCC_ISTAT ((u32*)(DANUBE_EBU_BASE_ADDR + 0x00A0))
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/*------------ CGU */
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#define DANUBE_CGU_BASE_ADDR 0xBF103000
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/* clock mux */
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#define DANUBE_CGU_SYS ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0010))
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#define DANUBE_CGU_IFCCR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0018))
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#define DANUBE_CGU_PCICR ((u32*)(DANUBE_CGU_BASE_ADDR + 0x0034))
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#define CLOCK_60M 60000000
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#define CLOCK_83M 83333333
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#define CLOCK_111M 111111111
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#define CLOCK_133M 133333333
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#define CLOCK_167M 166666667
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#define CLOCK_333M 333333333
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/*------------ CGU */
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#define DANUBE_PMU_BASE_ADDR (KSEG1 + 0x1F102000)
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#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
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#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
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/*------------ ICU */
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#define DANUBE_ICU_BASE_ADDR 0xBF880200
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#define DANUBE_ICU_IM0_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0000))
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#define DANUBE_ICU_IM0_IER ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0008))
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#define DANUBE_ICU_IM0_IOSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0010))
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#define DANUBE_ICU_IM0_IRSR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0018))
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#define DANUBE_ICU_IM0_IMR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0020))
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#define DANUBE_ICU_IM1_ISR ((u32*)(DANUBE_ICU_BASE_ADDR + 0x0028))
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#define DANUBE_ICU_OFFSET (DANUBE_ICU_IM1_ISR - DANUBE_ICU_IM0_ISR)
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/*------------ ETOP */
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#define DANUBE_PPE32_BASE_ADDR 0xBE180000
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#define ETHERNET_PACKET_DMA_BUFFER_SIZE 0x600
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#define DANUBE_PPE32_MEM_MAP (DANUBE_PPE32_BASE_ADDR + 0x10000 )
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#define MII_MODE 1
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#define REV_MII_MODE 2
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/* mdio access */
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#define DANUBE_PPE32_MDIO_ACC ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1804))
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#define MDIO_ACC_REQUEST 0x80000000
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#define MDIO_ACC_READ 0x40000000
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#define MDIO_ACC_ADDR_MASK 0x1f
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#define MDIO_ACC_ADDR_OFFSET 0x15
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#define MDIO_ACC_REG_MASK 0xff
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#define MDIO_ACC_REG_OFFSET 0x10
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#define MDIO_ACC_VAL_MASK 0xffff
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/* configuration */
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#define DANUBE_PPE32_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1808))
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#define PPE32_MII_MASK 0xfffffffc
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#define PPE32_MII_NORMAL 0x8
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#define PPE32_MII_REVERSE 0xe
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/* packet length */
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#define DANUBE_PPE32_IG_PLEN_CTRL ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1820))
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#define PPE32_PLEN_OVER 0x5ee
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#define PPE32_PLEN_UNDER 0x400000
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/* enet */
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#define DANUBE_PPE32_ENET_MAC_CFG ((u32*)(DANUBE_PPE32_MEM_MAP + 0x1840))
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#define PPE32_CGEN 0x800
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/*------------ DMA */
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#define DANUBE_DMA_BASE_ADDR 0xBE104100
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#define DANUBE_DMA_CS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x18))
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#define DANUBE_DMA_CIE ((u32*)(DANUBE_DMA_BASE_ADDR + 0x2C))
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#define DANUBE_DMA_IRNEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0xf4))
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#define DANUBE_DMA_CCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x1C))
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#define DANUBE_DMA_CIS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x28))
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#define DANUBE_DMA_CDLEN ((u32*)(DANUBE_DMA_BASE_ADDR + 0x24))
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#define DANUBE_DMA_PS ((u32*)(DANUBE_DMA_BASE_ADDR + 0x40))
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#define DANUBE_DMA_PCTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x44))
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#define DANUBE_DMA_CTRL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x10))
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#define DANUBE_DMA_CPOLL ((u32*)(DANUBE_DMA_BASE_ADDR + 0x14))
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#define DANUBE_DMA_CDBA ((u32*)(DANUBE_DMA_BASE_ADDR + 0x20))
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/*------------ PCI */
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#define PCI_CR_PR_BASE_ADDR (KSEG1 + 0x1E105400)
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#define PCI_CR_FCI_ADDR_MAP0 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C0))
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#define PCI_CR_FCI_ADDR_MAP1 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C4))
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#define PCI_CR_FCI_ADDR_MAP2 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00C8))
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#define PCI_CR_FCI_ADDR_MAP3 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00CC))
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#define PCI_CR_FCI_ADDR_MAP4 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D0))
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#define PCI_CR_FCI_ADDR_MAP5 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D4))
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#define PCI_CR_FCI_ADDR_MAP6 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00D8))
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#define PCI_CR_FCI_ADDR_MAP7 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00DC))
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#define PCI_CR_CLK_CTRL ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0000))
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#define PCI_CR_PCI_MOD ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0030))
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#define PCI_CR_PC_ARB ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0080))
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#define PCI_CR_FCI_ADDR_MAP11hg ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E4))
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#define PCI_CR_BAR11MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0044))
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#define PCI_CR_BAR12MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0048))
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#define PCI_CR_BAR13MASK ((u32*)(PCI_CR_PR_BASE_ADDR + 0x004C))
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#define PCI_CS_BASE_ADDR1 ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0010))
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#define PCI_CR_PCI_ADDR_MAP11 ((u32*)(PCI_CR_PR_BASE_ADDR + 0x0064))
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#define PCI_CR_FCI_BURST_LENGTH ((u32*)(PCI_CR_PR_BASE_ADDR + 0x00E8))
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#define PCI_CR_PCI_EOI ((u32*)(PCI_CR_PR_BASE_ADDR + 0x002C))
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#define PCI_CS_PR_BASE_ADDR (KSEG1 + 0x17000000)
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#define PCI_CS_STS_CMD ((u32*)(PCI_CS_PR_BASE_ADDR + 0x0004))
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#define PCI_MASTER0_REQ_MASK_2BITS 8
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#define PCI_MASTER1_REQ_MASK_2BITS 10
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#define PCI_MASTER2_REQ_MASK_2BITS 12
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#define INTERNAL_ARB_ENABLE_BIT 0
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/*------------ WDT */
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#define DANUBE_WDT_BASE_ADDR (KSEG1 + 0x1F880000)
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#define DANUBE_BIU_WDT_CR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F0))
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#define DANUBE_BIU_WDT_SR ((u32*)(DANUBE_WDT_BASE_ADDR + 0x03F8))
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#define DANUBE_BIU_WDT_CR_GEN (1 << 31)
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#define DANUBE_BIU_WDT_CR_DSEN (1 << 30)
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#define DANUBE_BIU_WDT_CR_LPEN (1 << 29)
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#define DANUBE_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1))
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#define DANUBE_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1))
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#define DANUBE_BIU_WDT_CR_PWL_SET(value) ((((1 << 2) - 1) & (value)) << 26)
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#define DANUBE_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16)
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#define DANUBE_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24)
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#define DANUBE_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0)
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/*------------ LED */
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#define DANUBE_LED_BASE_ADDR (KSEG1 + 0x1E100BB0)
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#define DANUBE_LED_CON0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0000))
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#define DANUBE_LED_CON1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0004))
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#define DANUBE_LED_CPU0 ((u32*)(DANUBE_LED_BASE_ADDR + 0x0008))
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#define DANUBE_LED_CPU1 ((u32*)(DANUBE_LED_BASE_ADDR + 0x000C))
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#define DANUBE_LED_AR ((u32*)(DANUBE_LED_BASE_ADDR + 0x0010))
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#define LED_CON0_SWU (1 << 31)
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#define LED_CON0_AD1 (1 << 25)
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#define LED_CON0_AD0 (1 << 24)
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#define DANUBE_LED_2HZ (0)
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#define DANUBE_LED_4HZ (1 << 23)
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#define DANUBE_LED_8HZ (2 << 23)
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#define DANUBE_LED_10HZ (3 << 23)
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#define DANUBE_LED_MASK (0xf << 23)
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#define DANUBE_LED_UPD_SRC_FPI (1 << 31)
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#define DANUBE_LED_UPD_MASK (3 << 30)
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#define DANUBE_LED_ADSL_SRC (3 << 24)
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#define DANUBE_LED_GROUP0 (1 << 0)
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#define DANUBE_LED_GROUP1 (1 << 1)
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#define DANUBE_LED_GROUP2 (1 << 2)
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#define DANUBE_LED_RISING 0
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#define DANUBE_LED_FALLING (1 << 26)
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#define DANUBE_LED_EDGE_MASK (1 << 26)
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/*------------ GPIO */
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#define DANUBE_GPIO_BASE_ADDR (0xBE100B00)
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#define DANUBE_GPIO_P0_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0010))
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#define DANUBE_GPIO_P1_OUT ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0040))
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#define DANUBE_GPIO_P0_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0014))
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#define DANUBE_GPIO_P1_IN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0044))
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#define DANUBE_GPIO_P0_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0018))
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#define DANUBE_GPIO_P1_DIR ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0048))
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#define DANUBE_GPIO_P0_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x001C))
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#define DANUBE_GPIO_P1_ALTSEL0 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x004C))
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#define DANUBE_GPIO_P0_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0020))
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#define DANUBE_GPIO_P1_ALTSEL1 ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0050))
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#define DANUBE_GPIO_P0_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0024))
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#define DANUBE_GPIO_P1_OD ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0054))
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#define DANUBE_GPIO_P0_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0028))
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#define DANUBE_GPIO_P1_STOFF ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0058))
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#define DANUBE_GPIO_P0_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x002C))
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#define DANUBE_GPIO_P1_PUDSEL ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x005C))
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#define DANUBE_GPIO_P0_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0030))
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#define DANUBE_GPIO_P1_PUDEN ((u32*)(DANUBE_GPIO_BASE_ADDR + 0x0060))
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/*------------ SSC */
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#define DANUBE_SSC1_BASE_ADDR (KSEG1 + 0x1e100800)
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#endif
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