125 lines
3 KiB
Diff
125 lines
3 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Date: Sat, 9 Jul 2016 15:26:44 +0200
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Subject: [PATCH] ath9k_hw: issue external reset for QCA955x
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The RTC interface on the SoC needs to be reset along with the rest of
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the WMAC.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/net/wireless/ath/ath9k/hw.c
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+++ b/drivers/net/wireless/ath/ath9k/hw.c
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@@ -1271,39 +1271,56 @@ void ath9k_hw_get_delta_slope_vals(struc
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*coef_exponent = coef_exp - 16;
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}
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-/* AR9330 WAR:
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- * call external reset function to reset WMAC if:
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- * - doing a cold reset
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- * - we have pending frames in the TX queues.
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- */
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-static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
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+static bool ath9k_hw_need_external_reset(struct ath_hw *ah, int type)
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{
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- int i, npend = 0;
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+ int i;
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- for (i = 0; i < AR_NUM_QCU; i++) {
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- npend = ath9k_hw_numtxpending(ah, i);
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- if (npend)
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- break;
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+ if (type == ATH9K_RESET_COLD)
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+ return true;
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+
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+ if (AR_SREV_9550(ah))
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+ return true;
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+
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+ /* AR9330 WAR:
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+ * call external reset function to reset WMAC if:
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+ * - doing a cold reset
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+ * - we have pending frames in the TX queues.
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+ */
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+ if (AR_SREV_9330(ah)) {
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+ for (i = 0; i < AR_NUM_QCU; i++) {
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+ if (ath9k_hw_numtxpending(ah, i))
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+ return true;
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+ }
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}
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- if (ah->external_reset &&
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- (npend || type == ATH9K_RESET_COLD)) {
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- int reset_err = 0;
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+ return false;
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+}
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- ath_dbg(ath9k_hw_common(ah), RESET,
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- "reset MAC via external reset\n");
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+static bool ath9k_hw_external_reset(struct ath_hw *ah, int type)
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+{
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+ int err;
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- reset_err = ah->external_reset();
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- if (reset_err) {
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- ath_err(ath9k_hw_common(ah),
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- "External reset failed, err=%d\n",
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- reset_err);
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- return false;
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- }
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+ if (!ah->external_reset || !ath9k_hw_need_external_reset(ah, type))
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+ return true;
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- REG_WRITE(ah, AR_RTC_RESET, 1);
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+ ath_dbg(ath9k_hw_common(ah), RESET,
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+ "reset MAC via external reset\n");
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+
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+ err = ah->external_reset();
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+ if (err) {
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+ ath_err(ath9k_hw_common(ah),
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+ "External reset failed, err=%d\n", err);
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+ return false;
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+ }
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+
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+ if (AR_SREV_9550(ah)) {
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+ REG_WRITE(ah, AR_RTC_RESET, 0);
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+ udelay(10);
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}
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+ REG_WRITE(ah, AR_RTC_RESET, 1);
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+ udelay(10);
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+
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return true;
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}
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@@ -1356,24 +1373,23 @@ static bool ath9k_hw_set_reset(struct at
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rst_flags |= AR_RTC_RC_MAC_COLD;
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}
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- if (AR_SREV_9330(ah)) {
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- if (!ath9k_hw_ar9330_reset_war(ah, type))
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- return false;
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- }
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-
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if (ath9k_hw_mci_is_enabled(ah))
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ar9003_mci_check_gpm_offset(ah);
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/* DMA HALT added to resolve ar9300 and ar9580 bus error during
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- * RTC_RC reg read
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+ * RTC_RC reg read. Also needed for AR9550 external reset
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*/
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- if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
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+ if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
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REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
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ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
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20 * AH_WAIT_TIMEOUT);
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- REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
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}
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+ ath9k_hw_external_reset(ah, type);
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+
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+ if (AR_SREV_9300(ah) || AR_SREV_9580(ah))
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+ REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
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+
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REG_WRITE(ah, AR_RTC_RC, rst_flags);
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REGWRITE_BUFFER_FLUSH(ah);
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