8dd455e3c4
Add more registers and flags to ar71x_regs.h for QCA955x and QCA956x SoCs. Values come from Qualcomm Atheros u-boot code. Patches can be merged into 622-MIPS-ath79-add-more-register-defines-for-QCA956x-SoC.patch Signed-off-by: Julien Dusser <julien.dusser@free.fr>
286 lines
7.7 KiB
C
286 lines
7.7 KiB
C
/*
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* Cisco Meraki MR18 board support
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*
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* Copyright (C) 2015 Chris Blake <chrisrblake93@gmail.com>
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* Copyright (C) 2015 Christian Lamparter <chunkeey@googlemail.com>
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* Copyright (C) 2015 Thomas Hebb <tommyhebb@gmail.com>
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*
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* Based on Cisco Meraki GPL Release r23-20150601 MR18 Device Config
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/ath9k_platform.h>
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#include <linux/platform/ar934x_nfc.h>
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#include <linux/platform_data/phy-at803x.h>
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#include <asm/mach-ath79/ath79.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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#include <linux/leds-nu801.h>
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#include <linux/pci.h>
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#include "common.h"
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#include "dev-eth.h"
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#include "pci.h"
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#include "dev-gpio-buttons.h"
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#include "dev-leds-gpio.h"
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#include "dev-nfc.h"
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#include "dev-wmac.h"
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#include "machtypes.h"
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#define MR18_GPIO_LED_POWER_WHITE 18
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#define MR18_GPIO_LED_POWER_ORANGE 21
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#define MR18_GPIO_BTN_RESET 17
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#define MR18_KEYS_POLL_INTERVAL 20 /* msecs */
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#define MR18_KEYS_DEBOUNCE_INTERVAL (3 * MR18_KEYS_POLL_INTERVAL)
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#define MR18_WAN_PHYADDR 3
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/* used for eth calibration */
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#define MR18_OTP_BASE (AR71XX_APB_BASE + 0x130000)
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#define MR18_OTP_SIZE (0x2000) /* just a guess */
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#define MR18_OTP_MEM_0_REG (0x0000)
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#define MR18_OTP_INTF2_REG (0x1008)
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#define MR18_OTP_STATUS0_REG (0x1018)
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#define MR18_OTP_STATUS0_EFUSE_VALID BIT(2)
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#define MR18_OTP_STATUS1_REG (0x101c)
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#define MR18_OTP_LDO_CTRL_REG (0x1024)
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#define MR18_OTP_LDO_STATUS_REG (0x102c)
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#define MR18_OTP_LDO_STATUS_POWER_ON BIT(0)
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static struct gpio_led MR18_leds_gpio[] __initdata = {
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{
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.name = "mr18:white:power",
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.gpio = MR18_GPIO_LED_POWER_WHITE,
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.active_low = 1,
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}, {
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.name = "mr18:orange:power",
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.gpio = MR18_GPIO_LED_POWER_ORANGE,
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.active_low = 0,
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},
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};
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static struct gpio_keys_button MR18_gpio_keys[] __initdata = {
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{
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.desc = "reset",
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.type = EV_KEY,
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.code = KEY_RESTART,
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.debounce_interval = MR18_KEYS_DEBOUNCE_INTERVAL,
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.gpio = MR18_GPIO_BTN_RESET,
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.active_low = 1,
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},
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};
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static struct led_nu801_template tricolor_led_template = {
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.device_name = "mr18",
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.name = "tricolor",
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.num_leds = 1,
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.cki = 11,
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.sdi = 12,
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.lei = -1,
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.ndelay = 500,
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.init_brightness = {
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LED_OFF,
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LED_OFF,
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LED_OFF,
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},
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.default_trigger = "none",
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.led_colors = { "red", "green", "blue" },
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};
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static struct led_nu801_platform_data tricolor_led_data = {
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.num_controllers = 1,
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.template = &tricolor_led_template,
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};
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static struct platform_device tricolor_leds = {
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.name = "leds-nu801",
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.id = -1,
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.dev.platform_data = &tricolor_led_data,
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};
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static int mr18_extract_sgmii_res_cal(void)
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{
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void __iomem *base;
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unsigned int reversed_sgmii_value;
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unsigned int otp_value, otp_per_val, rbias_per, read_data;
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unsigned int rbias_pos_or_neg;
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unsigned int sgmii_res_cal_value;
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int res_cal_val;
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base = ioremap_nocache(MR18_OTP_BASE, MR18_OTP_SIZE);
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if (!base)
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return -EIO;
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__raw_writel(0x7d, base + MR18_OTP_INTF2_REG);
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__raw_writel(0x00, base + MR18_OTP_LDO_CTRL_REG);
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while (__raw_readl(base + MR18_OTP_LDO_STATUS_REG) &
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MR18_OTP_LDO_STATUS_POWER_ON);
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__raw_readl(base + MR18_OTP_MEM_0_REG + 4);
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while (!(__raw_readl(base + MR18_OTP_STATUS0_REG) &
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MR18_OTP_STATUS0_EFUSE_VALID));
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read_data = __raw_readl(base + MR18_OTP_STATUS1_REG);
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iounmap(base);
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if (!(read_data & 0x1fff))
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return -ENODEV;
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if (read_data & 0x00001000)
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otp_value = (read_data & 0xfc0) >> 6;
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else
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otp_value = read_data & 0x3f;
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if (otp_value > 31) {
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otp_per_val = 63 - otp_value;
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rbias_pos_or_neg = 1;
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} else {
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otp_per_val = otp_value;
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rbias_pos_or_neg = 0;
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}
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rbias_per = otp_per_val * 15;
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if (rbias_pos_or_neg == 1)
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res_cal_val = (rbias_per + 34) / 21;
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else if (rbias_per > 34)
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res_cal_val = -((rbias_per - 34) / 21);
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else
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res_cal_val = (34 - rbias_per) / 21;
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sgmii_res_cal_value = (8 + res_cal_val) & 0xf;
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reversed_sgmii_value = (sgmii_res_cal_value & 8) >> 3;
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reversed_sgmii_value |= (sgmii_res_cal_value & 4) >> 1;
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reversed_sgmii_value |= (sgmii_res_cal_value & 2) << 1;
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reversed_sgmii_value |= (sgmii_res_cal_value & 1) << 3;
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printk(KERN_INFO "SGMII cal value = 0x%x\n", reversed_sgmii_value);
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return reversed_sgmii_value;
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}
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static void mr18_setup_qca955x_eth_serdes_cal(unsigned int sgmii_value)
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{
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void __iomem *ethbase, *pllbase;
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u32 t;
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ethbase = ioremap_nocache(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
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pllbase = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
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/* To Check the locking of the SGMII PLL */
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t = __raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
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t &= ~(QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK <<
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QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT);
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t |= (sgmii_value & QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK) <<
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QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT;
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__raw_writel(t, ethbase + QCA955X_GMAC_REG_SGMII_SERDES);
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__raw_writel(QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT |
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QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK |
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QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL,
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pllbase + QCA955X_PLL_ETH_SGMII_SERDES_REG);
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ath79_device_reset_clear(QCA955X_RESET_SGMII_ANALOG);
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ath79_device_reset_clear(QCA955X_RESET_SGMII);
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while (!(__raw_readl(ethbase + QCA955X_GMAC_REG_SGMII_SERDES) &
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QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS));
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iounmap(ethbase);
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iounmap(pllbase);
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}
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static struct ath9k_platform_data pci_main_wifi_data = {
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.led_pin = -1,
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};
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static struct ath9k_platform_data pci_scan_wifi_data = {
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.led_pin = -1,
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};
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static int mr18_dual_pci_plat_dev_init(struct pci_dev *dev)
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{
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/* The PCIE devices are attached to different busses but they
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* both share the same slot number. Checking the PCI_SLOT vals
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* does not work.
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*/
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switch (dev->bus->number) {
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case 0:
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dev->dev.platform_data = &pci_main_wifi_data;
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break;
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case 1:
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dev->dev.platform_data = &pci_scan_wifi_data;
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break;
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}
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return 0;
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}
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static void __init mr18_setup(void)
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{
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int res;
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/* NAND */
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ath79_nfc_set_ecc_mode(AR934X_NFC_ECC_SOFT_BCH);
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ath79_register_nfc();
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/* even though, the PHY is connected via RGMII,
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* the SGMII/SERDES PLLs need to be calibrated and locked.
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* Or else, the PHY won't be working for this platfrom.
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*
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* Figuring this out took such a long time, that we want to
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* point this quirk out, before someone wants to remove it.
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*/
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res = mr18_extract_sgmii_res_cal();
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if (res >= 0) {
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/* Setup SoC Eth Config */
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN |
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(3 << QCA955X_ETH_CFG_RXD_DELAY_SHIFT) |
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(3 << QCA955X_ETH_CFG_RDV_DELAY_SHIFT));
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/* MDIO Interface */
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ath79_register_mdio(0, 0x0);
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mr18_setup_qca955x_eth_serdes_cal(res);
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/* GMAC0 is connected to an Atheros AR8035-A */
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ath79_init_mac(ath79_eth0_data.mac_addr, NULL, 0);
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ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
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ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
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ath79_eth0_data.phy_mask = BIT(MR18_WAN_PHYADDR);
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ath79_eth0_pll_data.pll_1000 = 0xa6000000;
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ath79_eth0_pll_data.pll_100 = 0xa0000101;
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ath79_eth0_pll_data.pll_10 = 0x80001313;
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ath79_register_eth(0);
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} else {
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printk(KERN_ERR "failed to read EFUSE for ethernet cal\n");
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}
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/* LEDs and Buttons */
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platform_device_register(&tricolor_leds);
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ath79_register_leds_gpio(-1, ARRAY_SIZE(MR18_leds_gpio),
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MR18_leds_gpio);
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ath79_register_gpio_keys_polled(-1, MR18_KEYS_POLL_INTERVAL,
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ARRAY_SIZE(MR18_gpio_keys),
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MR18_gpio_keys);
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/* Clear RTC reset (Needed by SoC WiFi) */
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ath79_device_reset_clear(QCA955X_RESET_RTC);
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/* WiFi */
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ath79_register_wmac_simple();
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pci_main_wifi_data.eeprom_name = "pci_wmac0.eeprom";
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pci_scan_wifi_data.eeprom_name = "pci_wmac1.eeprom";
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ath79_pci_set_plat_dev_init(mr18_dual_pci_plat_dev_init);
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ath79_register_pci();
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}
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MIPS_MACHINE(ATH79_MACH_MR18, "MR18", "Meraki MR18", mr18_setup);
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