b50fd8c2b3
Register SPI controllers through device tree. We will wire up the clocks at a later stage. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
93 lines
3.1 KiB
Diff
93 lines
3.1 KiB
Diff
--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
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+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
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@@ -716,6 +716,27 @@ static struct board_info __initdata boar
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.ext_irq = 2,
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},
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};
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+
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+static struct board_info __initdata board_V2500V_BB = {
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+ .name = "V2500V_BB",
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+ .expected_cpu_id = 0x6348,
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+
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+ .has_uart0 = 1,
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+ .has_enet0 = 1,
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+ .has_enet1 = 1,
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+ .has_pci = 1,
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+
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+ .enet0 = {
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+ .has_phy = 1,
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+ .use_internal_phy = 1,
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+ },
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+ .enet1 = {
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+ .has_phy = 1,
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+ .phy_id = 0,
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+ .force_speed_100 = 1,
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+ .force_duplex_full = 1,
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+ },
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+};
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#endif /* CONFIG_BCM63XX_CPU_6348 */
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/*
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@@ -1048,6 +1069,7 @@ static const struct board_info __initcon
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&board_96348_D4PW,
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&board_spw500v,
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&board_96348sv,
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+ &board_V2500V_BB,
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6358
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@@ -1087,6 +1109,7 @@ static struct of_device_id const bcm963x
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{ .compatible = "brcm,bcm96348gw-10", .data = &board_96348gw_10, },
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{ .compatible = "brcm,bcm96348gw-11", .data = &board_96348gw_11, },
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{ .compatible = "brcm,bcm96348gw-a", .data = &board_96348gw_a, },
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+ { .compatible = "bt,v2500v-bb", .data = &board_V2500V_BB, },
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{ .compatible = "d-link,dsl-2640b-b", .data = &board_96348_D4PW, },
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{ .compatible = "davolink,dv-201amr", .data = &board_DV201AMR, },
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{ .compatible = "dynalink,rta1025w", .data = &board_rta1025w_16, },
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@@ -1146,6 +1169,22 @@ void __init board_bcm963xx_init(void)
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val &= MPI_CSBASE_BASE_MASK;
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}
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boot_addr = (u8 *)KSEG1ADDR(val);
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+ pr_info("Boot address 0x%08x\n",(unsigned int)boot_addr);
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+
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+ /* BT Voyager 2500V (RTA1046VW PCB) has 8 Meg flash used as two */
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+ /* banks of 4 Meg. The byte at 0xBF800000 identifies the back to use.*/
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+ /* Loading firmware from the CFE Prompt always loads to Bank 0 */
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+ /* Do an early check of CFE and then select bank 0 */
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+
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+ if (boot_addr == (u8 *)0xbf800000) {
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+ u8 *tmp_boot_addr = (u8*)0xbfc00000;
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+
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+ bcm63xx_nvram_init(tmp_boot_addr + BCM963XX_NVRAM_OFFSET);
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+ if (!strcmp(bcm63xx_nvram_get_name(), "V2500V_BB")) {
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+ pr_info("V2500V: nvram bank 0\n");
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+ boot_addr = tmp_boot_addr;
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+ }
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+ }
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/* dump cfe version */
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cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET;
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--- a/arch/mips/bcm63xx/dev-flash.c
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+++ b/arch/mips/bcm63xx/dev-flash.c
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@@ -21,6 +21,7 @@
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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+#include <bcm63xx_board.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_dev_flash.h>
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#include <bcm63xx_dev_hsspi.h>
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@@ -261,6 +262,13 @@ int __init bcm63xx_flash_register(int nu
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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+ /* BT Voyager 2500V has 8 Meg flash in two 4 Meg banks */
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+ /* Loading from CFE always uses Bank 0 */
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+ if (!strcmp(board_get_name(), "V2500V_BB")) {
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+ pr_info("V2500V: Start in Bank 0\n");
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+ val = val + 0x400000; // Select Bank 0 start address
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+ }
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+
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mtd_resources[0].start = val;
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mtd_resources[0].end = 0x1FFFFFFF;
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}
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