77 lines
1.8 KiB
Diff
77 lines
1.8 KiB
Diff
From ce6cb947b9535b2d81717925cb6a3bc9f8500f44 Mon Sep 17 00:00:00 2001
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From: Matthew McClintock <mmcclint@codeaurora.org>
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Date: Thu, 17 Mar 2016 15:01:09 -0500
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Subject: [PATCH 28/37] qcom: ipq4019: add cpu operating points for cpufreq
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support
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This adds some operating points for cpu frequeny scaling
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Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
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---
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arch/arm/boot/dts/qcom-ipq4019.dtsi | 34 ++++++++++++++++++++++++++--------
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1 file changed, 26 insertions(+), 8 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
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@@ -40,14 +40,7 @@
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reg = <0x0>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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- operating-points = <
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- /* kHz uV (fixed) */
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- 48000 1100000
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- 200000 1100000
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- 500000 1100000
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- 666000 1100000
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- >;
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- clock-latency = <256000>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@1 {
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@@ -59,6 +52,7 @@
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reg = <0x1>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@2 {
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@@ -70,6 +64,7 @@
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reg = <0x2>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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};
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cpu@3 {
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@@ -81,6 +76,29 @@
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reg = <0x3>;
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clocks = <&gcc GCC_APPS_CLK_SRC>;
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clock-frequency = <0>;
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+ operating-points-v2 = <&cpu0_opp_table>;
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+ };
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+ };
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+
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+ cpu0_opp_table: opp_table0 {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp@48000000 {
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+ opp-hz = /bits/ 64 <48000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp@200000000 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp@500000000 {
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+ opp-hz = /bits/ 64 <500000000>;
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+ clock-latency-ns = <256000>;
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+ };
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+ opp@666000000 {
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+ opp-hz = /bits/ 64 <666000000>;
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+ clock-latency-ns = <256000>;
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};
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};
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