83 lines
2.4 KiB
Diff
83 lines
2.4 KiB
Diff
diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c
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index 47fb70f..5cc5d25 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock.c
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@@ -14,12 +14,17 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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+__weak void clock_init_sec(void)
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+{
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+}
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+
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int clock_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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clock_init_safe();
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#endif
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clock_init_uart();
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+ clock_init_sec();
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return 0;
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}
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diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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index 4501884..d0085e8 100644
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--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
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@@ -45,6 +45,19 @@ void clock_init_safe(void)
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}
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#endif
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+void clock_init_sec(void)
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+{
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+ struct sunxi_ccm_reg * const ccm =
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+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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+
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+#ifdef CONFIG_MACH_SUN8I_H3
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+ setbits_le32(&ccm->ccu_sec_switch,
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+ CCM_SEC_SWITCH_MBUS_NONSEC |
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+ CCM_SEC_SWITCH_BUS_NONSEC |
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+ CCM_SEC_SWITCH_PLL_NONSEC);
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+#endif
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+}
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+
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void clock_init_uart(void)
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{
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#if CONFIG_CONS_INDEX < 5
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diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
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index 8ca58ae..6c0573f 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock.h
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@@ -30,6 +30,7 @@ int clock_init(void);
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int clock_twi_onoff(int port, int state);
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void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
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void clock_init_safe(void);
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+void clock_init_sec(void);
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void clock_init_uart(void);
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#endif
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diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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index 5c76275..554d858 100644
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--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
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@@ -137,6 +137,8 @@ struct sunxi_ccm_reg {
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u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
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u32 reserved24;
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u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
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+ u32 reserved25[5];
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+ u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
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};
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/* apb2 bit field */
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@@ -375,6 +377,11 @@ struct sunxi_ccm_reg {
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#define CCM_DE_CTRL_PLL10 (5 << 24)
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#define CCM_DE_CTRL_GATE (1 << 31)
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+/* CCU security switch, H3 only */
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+#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
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+#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
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+#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0)
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+
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#ifndef __ASSEMBLY__
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void clock_set_pll1(unsigned int hz);
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void clock_set_pll3(unsigned int hz);
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