70 lines
2 KiB
Diff
70 lines
2 KiB
Diff
From 538d4a6ca5f41039d906f28be82e0f4d26ec8ac9 Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
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Date: Mon, 23 Dec 2013 00:32:44 -0300
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Subject: [PATCH] ARM: sunxi: dt: add nodes for the mbus clock
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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mbus is the memory bus clock, and it is present on both sun5i and sun7i
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machines. Its register layout is compatible with the mod0 one.
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Signed-off-by: Emilio López <emilio@elopez.com.ar>
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Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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---
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arch/arm/boot/dts/sun5i-a10s.dtsi | 8 ++++++++
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arch/arm/boot/dts/sun5i-a13.dtsi | 8 ++++++++
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arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
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3 files changed, 24 insertions(+)
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--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
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@@ -257,6 +257,14 @@
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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+
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+ mbus_clk: clk@01c2015c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2015c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mbus";
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+ };
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};
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soc@01c00000 {
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--- a/arch/arm/boot/dts/sun5i-a13.dtsi
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+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
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@@ -258,6 +258,14 @@
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "ir0";
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};
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+
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+ mbus_clk: clk@01c2015c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2015c 0x4>;
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+ clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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+ clock-output-names = "mbus";
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+ };
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};
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soc@01c00000 {
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--- a/arch/arm/boot/dts/sun7i-a20.dtsi
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+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
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@@ -290,6 +290,14 @@
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clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
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clock-output-names = "spi3";
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};
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+
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+ mbus_clk: clk@01c2015c {
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+ #clock-cells = <0>;
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+ compatible = "allwinner,sun4i-mod0-clk";
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+ reg = <0x01c2015c 0x4>;
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+ clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
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+ clock-output-names = "mbus";
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+ };
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};
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soc@01c00000 {
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