51 lines
1.4 KiB
Diff
51 lines
1.4 KiB
Diff
From 6dd612e3d7e0c76f863efaddae4738fadc461f72 Mon Sep 17 00:00:00 2001
|
|
From: Chen-Yu Tsai <wens@csie.org>
|
|
Date: Tue, 24 Dec 2013 21:26:18 +0800
|
|
Subject: [PATCH] ARM: dts: sun7i: external clock outputs
|
|
|
|
This commit adds the two external clock outputs available on A20 to
|
|
its device tree. A dummy fixed factor clock is also added to serve as
|
|
the first input of the clock outputs, which according to AW's A20 user
|
|
manual, is the 24MHz oscillator divided by 750.
|
|
|
|
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
|
|
---
|
|
arch/arm/boot/dts/sun7i-a20.dtsi | 27 +++++++++++++++++++++++++++
|
|
1 file changed, 27 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
|
|
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
|
|
@@ -312,6 +312,33 @@
|
|
clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
|
|
clock-output-names = "mbus";
|
|
};
|
|
+
|
|
+ /*
|
|
+ * Dummy clock used by output clocks
|
|
+ */
|
|
+ osc24M_32k: osc24M_32k {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "fixed-factor-clock";
|
|
+ clock-div = <750>;
|
|
+ clock-mult = <1>;
|
|
+ clocks = <&osc24M>;
|
|
+ };
|
|
+
|
|
+ clk_out_a: clk@01c201f0 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun7i-a20-out-clk";
|
|
+ reg = <0x01c201f0 0x4>;
|
|
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
|
|
+ clock-output-names = "clk_out_a";
|
|
+ };
|
|
+
|
|
+ clk_out_b: clk@01c201f4 {
|
|
+ #clock-cells = <0>;
|
|
+ compatible = "allwinner,sun7i-a20-out-clk";
|
|
+ reg = <0x01c201f4 0x4>;
|
|
+ clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
|
|
+ clock-output-names = "clk_out_b";
|
|
+ };
|
|
};
|
|
|
|
timer {
|