d2a2eb7e48
This driver has been cherry-picked and backported from the following LKML thread: *https://lkml.org/lkml/2015/5/26/744 It also updates the DT accordingly. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 45831
52 lines
1.6 KiB
Diff
52 lines
1.6 KiB
Diff
From 0f9605d9409b77a89daef91cc68239fc2ff50457 Mon Sep 17 00:00:00 2001
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From: Mathieu Olivari <mathieu@codeaurora.org>
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Date: Fri, 8 May 2015 16:51:25 -0700
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Subject: [PATCH 5/8] net: stmmac: ipq806x: document device tree bindings
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Add the device tree bindings documentation for the QCA IPQ806x
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variant of the Synopsys DesignWare MAC.
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Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
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---
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.../devicetree/bindings/net/ipq806x-dwmac.txt | 35 ++++++++++++++++++++++
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1 file changed, 35 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
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@@ -0,0 +1,35 @@
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+* IPQ806x DWMAC Ethernet controller
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+
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+The device inherits all the properties of the dwmac/stmmac devices
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+described in the file net/stmmac.txt with the following changes.
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+
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+Required properties:
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+
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+- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
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+ and any applicable more detailed version number
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+ described in net/stmmac.txt
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+
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+- qcom,nss-common: should contain a phandle to a syscon device mapping the
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+ nss-common registers.
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+
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+- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
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+ qsgmii-csr registers.
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+
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+Example:
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+
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+ gmac: ethernet@37000000 {
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+ device_type = "network";
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+ compatible = "qcom,ipq806x-gmac";
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+ reg = <0x37000000 0x200000>;
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+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "macirq";
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+
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+ qcom,nss-common = <&nss_common>;
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+ qcom,qsgmii-csr = <&qsgmii_csr>;
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+
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+ clocks = <&gcc GMAC_CORE1_CLK>;
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+ clock-names = "stmmaceth";
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+
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+ resets = <&gcc GMAC_CORE1_RESET>;
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+ reset-names = "stmmaceth";
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+ };
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