85 lines
2.1 KiB
Diff
85 lines
2.1 KiB
Diff
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
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+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
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@@ -214,11 +214,21 @@ static struct map_desc cns3420_io_desc[]
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static void __init cns3420_map_io(void)
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{
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cns3xxx_map_io();
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+ cns3xxx_pcie_iotable_init();
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iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
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cns3420_early_serial_setup();
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}
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+static int __init cns3420vb_pcie_init(void)
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+{
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+ if (!machine_is_cns3420vb())
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+ return 0;
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+
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+ return cns3xxx_pcie_init();
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+}
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+subsys_initcall(cns3420vb_pcie_init);
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+
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MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
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.atag_offset = 0x100,
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.map_io = cns3420_map_io,
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--- a/arch/arm/mach-cns3xxx/core.h
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+++ b/arch/arm/mach-cns3xxx/core.h
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@@ -12,6 +12,8 @@
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#define __CNS3XXX_CORE_H
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extern struct sys_timer cns3xxx_timer;
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+extern void cns3xxx_pcie_iotable_init(void);
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+
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#ifdef CONFIG_CACHE_L2X0
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void __init cns3xxx_l2x0_init(void);
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@@ -21,6 +23,7 @@ static inline void cns3xxx_l2x0_init(voi
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void __init cns3xxx_map_io(void);
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void __init cns3xxx_init_irq(void);
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+int __init cns3xxx_pcie_init(void);
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void cns3xxx_power_off(void);
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void cns3xxx_restart(char, const char *);
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--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -456,7 +456,18 @@ static int cns3xxx_pcie_abort_handler(un
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return 0;
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}
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-static int __init cns3xxx_pcie_init(void)
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+
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+void __init cns3xxx_pcie_iotable_init()
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+{
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+ int i;
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+
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+ for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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+ iotable_init(cns3xxx_pcie[i].cfg_bases,
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+ ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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+ }
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+}
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+
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+int __init cns3xxx_pcie_init(void)
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{
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int i;
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@@ -467,15 +478,14 @@ static int __init cns3xxx_pcie_init(void
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"imprecise external abort");
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for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
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- iotable_init(cns3xxx_pcie[i].cfg_bases,
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- ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
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cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
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- cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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- pci_common_init(&cns3xxx_pcie[i].hw_pci);
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+ if (cns3xxx_pcie[i].linked) {
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+ cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
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+ pci_common_init(&cns3xxx_pcie[i].hw_pci);
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+ }
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}
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pci_assign_unassigned_resources();
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return 0;
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}
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-device_initcall(cns3xxx_pcie_init);
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