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openwrtv4/target/linux/ar71xx/patches-3.6/609-MIPS-ath79-ap136-fixes.patch
Gabor Juhos 64d31e6c6b ar71xx: register the second ethernet interface on the AP136 
Also fix the default network configuration
according to the new setup.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>

SVN-Revision: 34854
2012-12-22 12:12:50 +00:00

199 lines
5.4 KiB
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--- a/arch/mips/ath79/mach-ap136.c
+++ b/arch/mips/ath79/mach-ap136.c
@@ -1,5 +1,5 @@
/*
- * Qualcomm Atheros AP136 reference board support
+ * Atheros AP136 reference board support
*
* Copyright (c) 2012 Qualcomm Atheros
* Copyright (c) 2012 Gabor Juhos <juhosg@openwrt.org>
@@ -18,23 +18,27 @@
*
*/
-#include <linux/pci.h>
-#include <linux/ath9k_platform.h>
+#include <linux/platform_device.h>
+#include <linux/ar8216_platform.h>
-#include "machtypes.h"
+#include <asm/mach-ath79/ar71xx_regs.h>
+
+#include "common.h"
+#include "dev-ap9x-pci.h"
#include "dev-gpio-buttons.h"
+#include "dev-eth.h"
#include "dev-leds-gpio.h"
-#include "dev-spi.h"
+#include "dev-m25p80.h"
#include "dev-usb.h"
#include "dev-wmac.h"
-#include "pci.h"
+#include "machtypes.h"
-#define AP136_GPIO_LED_STATUS_RED 14
-#define AP136_GPIO_LED_STATUS_GREEN 19
#define AP136_GPIO_LED_USB 4
-#define AP136_GPIO_LED_WLAN_2G 13
#define AP136_GPIO_LED_WLAN_5G 12
+#define AP136_GPIO_LED_WLAN_2G 13
+#define AP136_GPIO_LED_STATUS_RED 14
#define AP136_GPIO_LED_WPS_RED 15
+#define AP136_GPIO_LED_STATUS_GREEN 19
#define AP136_GPIO_LED_WPS_GREEN 20
#define AP136_GPIO_BTN_WPS 16
@@ -43,8 +47,10 @@
#define AP136_KEYS_POLL_INTERVAL 20 /* msecs */
#define AP136_KEYS_DEBOUNCE_INTERVAL (3 * AP136_KEYS_POLL_INTERVAL)
-#define AP136_WMAC_CALDATA_OFFSET 0x1000
-#define AP136_PCIE_CALDATA_OFFSET 0x5000
+#define AP136_MAC0_OFFSET 0
+#define AP136_MAC1_OFFSET 6
+#define AP136_WMAC_CALDATA_OFFSET 0x1000
+#define AP136_PCIE_CALDATA_OFFSET 0x5000
static struct gpio_led ap136_leds_gpio[] __initdata = {
{
@@ -98,63 +104,106 @@ static struct gpio_keys_button ap136_gpi
},
};
-static struct ath79_spi_controller_data ap136_spi0_data = {
- .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
- .cs_line = 0,
+static struct ar8327_pad_cfg ap136_ar8327_pad0_cfg = {
+ .mode = AR8327_PAD_MAC_RGMII,
+ .txclk_delay_en = true,
+ .rxclk_delay_en = true,
+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
};
-static struct spi_board_info ap136_spi_info[] = {
- {
- .bus_num = 0,
- .chip_select = 0,
- .max_speed_hz = 25000000,
- .modalias = "mx25l6405d",
- .controller_data = &ap136_spi0_data,
- }
+static struct ar8327_pad_cfg ap136_ar8327_pad6_cfg = {
+ .mode = AR8327_PAD_MAC_SGMII,
+ .txclk_delay_en = false,
+ .rxclk_delay_en = true,
+ .txclk_delay_sel = AR8327_CLK_DELAY_SEL0,
+ .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
};
-static struct ath79_spi_platform_data ap136_spi_data = {
- .bus_num = 0,
- .num_chipselect = 1,
+static struct ar8327_platform_data ap136_ar8327_data = {
+ .pad0_cfg = &ap136_ar8327_pad0_cfg,
+ .pad6_cfg = &ap136_ar8327_pad6_cfg,
+ .port0_cfg = {
+ .force_link = 1,
+ .speed = AR8327_PORT_SPEED_1000,
+ .duplex = 1,
+ .txpause = 1,
+ .rxpause = 1,
+ },
+ .port6_cfg = {
+ .force_link = 1,
+ .speed = AR8327_PORT_SPEED_1000,
+ .duplex = 1,
+ .txpause = 1,
+ .rxpause = 1,
+ },
};
-#ifdef CONFIG_PCI
-static struct ath9k_platform_data ap136_ath9k_data;
+static struct mdio_board_info ap136_mdio0_info[] = {
+ {
+ .bus_id = "ag71xx-mdio.0",
+ .phy_addr = 0,
+ .platform_data = &ap136_ar8327_data,
+ },
+};
-static int ap136_pci_plat_dev_init(struct pci_dev *dev)
+static void __init ap136_gmac_setup(void)
{
- if (dev->bus->number == 1 && (PCI_SLOT(dev->devfn)) == 0)
- dev->dev.platform_data = &ap136_ath9k_data;
+ void __iomem *base;
+ u32 t;
- return 0;
-}
+ base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
-static void __init ap136_pci_init(u8 *eeprom)
-{
- memcpy(ap136_ath9k_data.eeprom_data, eeprom,
- sizeof(ap136_ath9k_data.eeprom_data));
+ t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
+
+ t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
+ t |= QCA955X_ETH_CFG_RGMII_EN;
+
+ __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
- ath79_pci_set_plat_dev_init(ap136_pci_plat_dev_init);
- ath79_register_pci();
+ iounmap(base);
}
-#else
-static inline void ap136_pci_init(void) {}
-#endif /* CONFIG_PCI */
static void __init ap136_setup(void)
{
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
+ ath79_register_m25p80(NULL);
+
ath79_register_leds_gpio(-1, ARRAY_SIZE(ap136_leds_gpio),
ap136_leds_gpio);
ath79_register_gpio_keys_polled(-1, AP136_KEYS_POLL_INTERVAL,
ARRAY_SIZE(ap136_gpio_keys),
ap136_gpio_keys);
- ath79_register_spi(&ap136_spi_data, ap136_spi_info,
- ARRAY_SIZE(ap136_spi_info));
+
ath79_register_usb();
- ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET);
- ap136_pci_init(art + AP136_PCIE_CALDATA_OFFSET);
+ ath79_register_wmac(art + AP136_WMAC_CALDATA_OFFSET, NULL);
+ ap91_pci_init(art + AP136_PCIE_CALDATA_OFFSET, NULL);
+
+ ap136_gmac_setup();
+
+ ath79_register_mdio(0, 0x0);
+
+ ath79_init_mac(ath79_eth0_data.mac_addr, art + AP136_MAC0_OFFSET, 0);
+
+ mdiobus_register_board_info(ap136_mdio0_info,
+ ARRAY_SIZE(ap136_mdio0_info));
+
+ /* GMAC0 is connected to GMAC0 of the AR8327 switch via RGMII */
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = BIT(0);
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
+ ath79_eth0_pll_data.pll_1000 = 0xa6000000;
+
+ ath79_register_eth(0);
+
+ /* GMAC1 is connected to GMAC6 of the AR8327 switch via SGMII */
+ ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
+ ath79_eth1_data.speed = SPEED_1000;
+ ath79_eth1_data.duplex = DUPLEX_FULL;
+ ath79_eth1_pll_data.pll_1000 = 0x03000101;
+
+ ath79_register_eth(1);
}
MIPS_MACHINE(ATH79_MACH_AP136, "AP136", "Atheros AP136 reference board",
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