f6dfeee3fe
Certain board revisions of the GW52xx support an SPI host controller with a single chip-select going to an off board connector. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Pushpal Sidhu <psidhu@gateworks.com> SVN-Revision: 48009
35 lines
1,007 B
Diff
35 lines
1,007 B
Diff
Index: linux-4.3/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
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===================================================================
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--- linux-4.3.orig/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi 2015-12-18 10:39:44.899158318 -0800
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+++ linux-4.3/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi 2015-12-18 10:43:27.000000000 -0800
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@@ -158,6 +158,14 @@
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<&clks IMX6QDL_CLK_PLL3_USB_OTG>;
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};
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+&ecspi3 {
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+ fsl,spi-num-chipselects = <1>;
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+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_ecspi3>;
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+ status = "okay";
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+};
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+
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet>;
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@@ -357,6 +365,15 @@
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>;
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};
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+ pinctrl_ecspi3: escpi3grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
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+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
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+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
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+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
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+ >;
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+ };
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+
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
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