0d9f760f27
Includes memory allocation fixes as well as several networking fixes. Signed-off-by: Jonas Gorski <jogo@openwrt.org> SVN-Revision: 37103
35 lines
1.3 KiB
Diff
35 lines
1.3 KiB
Diff
From 48cf6bc7019d418e18831214731a55ec7320abb3 Mon Sep 17 00:00:00 2001
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From: John Crispin <blogic@openwrt.org>
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Date: Thu, 21 Mar 2013 19:01:49 +0100
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Subject: [PATCH 102/164] MIPS: ralink: add RT3352 register defines
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Add a few missing defines that are needed to make USB and clock detection work
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on the RT3352.
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Signed-off-by: John Crispin <blogic@openwrt.org>
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Acked-by: Gabor Juhos <juhosg@openwrt.org>
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Patchwork: http://patchwork.linux-mips.org/patch/5166/
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---
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arch/mips/include/asm/mach-ralink/rt305x.h | 13 +++++++++++++
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1 file changed, 13 insertions(+)
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--- a/arch/mips/include/asm/mach-ralink/rt305x.h
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+++ b/arch/mips/include/asm/mach-ralink/rt305x.h
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@@ -136,4 +136,17 @@ static inline int soc_is_rt5350(void)
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#define RT305X_GPIO_MODE_SDRAM BIT(8)
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#define RT305X_GPIO_MODE_RGMII BIT(9)
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+#define RT3352_SYSC_REG_SYSCFG0 0x010
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+#define RT3352_SYSC_REG_SYSCFG1 0x014
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+#define RT3352_SYSC_REG_CLKCFG1 0x030
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+#define RT3352_SYSC_REG_RSTCTRL 0x034
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+#define RT3352_SYSC_REG_USB_PS 0x05c
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+
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+#define RT3352_CLKCFG0_XTAL_SEL BIT(20)
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+#define RT3352_CLKCFG1_UPHY0_CLK_EN BIT(18)
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+#define RT3352_CLKCFG1_UPHY1_CLK_EN BIT(20)
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+#define RT3352_RSTCTRL_UHST BIT(22)
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+#define RT3352_RSTCTRL_UDEV BIT(25)
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+#define RT3352_SYSCFG1_USB0_HOST_MODE BIT(10)
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+
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#endif
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