7b6e01d389
Refresh patches. Runtime tested: ar71xx - Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
23 lines
958 B
Diff
23 lines
958 B
Diff
--- a/drivers/pci/probe.c
|
|
+++ b/drivers/pci/probe.c
|
|
@@ -2015,7 +2015,8 @@ static void pcie_write_mrrs(struct pci_d
|
|
/* In the "safe" case, do not configure the MRRS. There appear to be
|
|
* issues with setting MRRS to 0 on a number of devices.
|
|
*/
|
|
- if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
|
|
+ if (pcie_bus_config != PCIE_BUS_PERFORMANCE &&
|
|
+ pcie_bus_config != PCIE_BUS_PEER2PEER)
|
|
return;
|
|
|
|
/* For Max performance, the MRRS must be set to the largest supported
|
|
--- a/include/linux/pci.h
|
|
+++ b/include/linux/pci.h
|
|
@@ -783,7 +783,7 @@ enum pcie_bus_config_types {
|
|
PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
|
|
PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
|
|
PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
|
|
- PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
|
|
+ PCIE_BUS_PEER2PEER, /* set MPS and MRSS to 128 for all devices */
|
|
};
|
|
|
|
extern enum pcie_bus_config_types pcie_bus_config;
|