a23da431dc
Add VR9 specific usb initialization bits from ltq-hcd to platform initialization. This patch is more of a proof-of-concept than production quality since the initialization registers are different on other lantiq platforms. Signed-off-by: Antti Seppälä <a.seppala@gmail.com> Signed-off-by: Vincent Pelletier <plr.vincent@gmail.com> SVN-Revision: 44672
95 lines
2.7 KiB
Diff
95 lines
2.7 KiB
Diff
--- a/arch/mips/lantiq/xway/reset.c 2015-02-09 18:23:01.837007936 +0200
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+++ b/arch/mips/lantiq/xway/reset.c 2015-02-09 19:16:43.006081435 +0200
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@@ -44,6 +44,37 @@
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#define RCU_BOOT_SEL(x) ((x >> 18) & 0x7)
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#define RCU_BOOT_SEL_XRX200(x) (((x >> 17) & 0xf) | ((x >> 8) & 0x10))
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+/* dwc2 USB configuration registers */
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+#define RCU_USB1CFG 0x0018
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+#define RCU_USB2CFG 0x0034
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+
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+/* USB DMA endianness bits */
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+#define RCU_USBCFG_HDSEL_BIT BIT(11)
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+#define RCU_USBCFG_HOST_END_BIT BIT(10)
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+#define RCU_USBCFG_SLV_END_BIT BIT(9)
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+
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+/* USB reset bits */
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+#define RCU_USBRESET 0x0010
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+
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+#define USBRESET_BIT BIT(4)
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+
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+#define RCU_USBRESET2 0x0048
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+
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+#define USB1RESET_BIT BIT(4)
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+#define USB2RESET_BIT BIT(5)
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+
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+#define RCU_CFG1A 0x0038
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+#define RCU_CFG1B 0x003C
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+
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+/* USB PMU devices */
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+#define PMU_AHBM BIT(15)
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+#define PMU_USB0 BIT(6)
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+#define PMU_USB1 BIT(27)
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+
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+/* USB PHY PMU devices */
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+#define PMU_USB0_P BIT(0)
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+#define PMU_USB1_P BIT(26)
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+
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/* remapped base addr of the reset control unit */
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static void __iomem *ltq_rcu_membase;
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static struct device_node *ltq_rcu_np;
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@@ -200,6 +231,45 @@
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unreachable();
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}
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+static void ltq_usb_init(void)
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+{
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+ /* Power for USB cores 1 & 2 */
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+ ltq_pmu_enable(PMU_AHBM);
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+ ltq_pmu_enable(PMU_USB0);
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+ ltq_pmu_enable(PMU_USB1);
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+
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1A) | BIT(0), RCU_CFG1A);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_CFG1B) | BIT(0), RCU_CFG1B);
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+
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+ /* Enable USB PHY power for cores 1 & 2 */
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+ ltq_pmu_enable(PMU_USB0_P);
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+ ltq_pmu_enable(PMU_USB1_P);
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+
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+ /* Configure cores to host mode */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_HDSEL_BIT,
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+ RCU_USB1CFG);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USB2CFG) & ~RCU_USBCFG_HDSEL_BIT,
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+ RCU_USB2CFG);
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+
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+ /* Select DMA endianness (Host-endian: big-endian) */
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+ ltq_rcu_w32((ltq_rcu_r32(RCU_USB1CFG) & ~RCU_USBCFG_SLV_END_BIT)
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+ | RCU_USBCFG_HOST_END_BIT, RCU_USB1CFG);
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+ ltq_rcu_w32(ltq_rcu_r32((RCU_USB2CFG) & ~RCU_USBCFG_SLV_END_BIT)
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+ | RCU_USBCFG_HOST_END_BIT, RCU_USB2CFG);
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+
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+ /* Hard reset USB state machines */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) | USBRESET_BIT, RCU_USBRESET);
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+ udelay(50 * 1000);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET) & ~USBRESET_BIT, RCU_USBRESET);
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+
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+ /* Soft reset USB state machines */
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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+ | USB1RESET_BIT | USB2RESET_BIT, RCU_USBRESET2);
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+ udelay(50 * 1000);
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+ ltq_rcu_w32(ltq_rcu_r32(RCU_USBRESET2)
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+ & ~(USB1RESET_BIT | USB2RESET_BIT), RCU_USBRESET2);
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+}
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+
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static int __init mips_reboot_setup(void)
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{
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struct resource res;
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@@ -223,6 +293,8 @@
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if (!ltq_rcu_membase)
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panic("Failed to remap core memory");
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+ ltq_usb_init();
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+
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_machine_restart = ltq_machine_restart;
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_machine_halt = ltq_machine_halt;
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pm_power_off = ltq_machine_power_off;
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